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ORCIDSteve Wilton
Steven J. E. Wilton
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- affiliation: University of British Columbia, Vancouver, Canada
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2020 – today
- 2024
[j46]Chris Keilbart
, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 17(2): 33:1-33:32 (2024)- [c129]Behnam Ghavami, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters. IOLTS 2024: 1-7 - [c128]Behnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton:
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. ISQED 2024: 1-7 - [c127]Behnam Ghavami, Mahdi Sajadi, Lesley Shannon, Steve Wilton:
Boosting Multiple Multipliers Packing on FPGA DSP Blocks via Truncation and Compensation-based Approximation. ISVLSI 2024: 222-227 - [c126]Andrew David Gunter, Maya Thomas, Nikhil Pratap Ghanathe, Steven J. E. Wilton:
Enabling Risk Management of Machine Learning Predictions for FPGA Routability. MLCAD 2024: 31:1-31:9 - [c125]Andrew David Gunter, Steven J. E. Wilton:
Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups. MLCAD 2024: 32:1-32:8 - [i8]Behnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton:
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization. CoRR abs/2404.02947 (2024) - [i7]Nikhil Pratap Ghanathe, Steve Wilton:
QUTE: Quantifying Uncertainty in TinyML models with Early-exit-assisted ensembles. CoRR abs/2404.12599 (2024) - [i6]Behnam Ghavami, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton:
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters. CoRR abs/2407.04964 (2024) - 2023
- [c124]Nikhil Pratap Ghanathe, Steve Wilton:
T-RecX: Tiny-Resource Efficient Convolutional neural networks with early-eXit. CF 2023: 123-133 - [c123]Andrew David Gunter, Steven J. E. Wilton:
A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. FCCM 2023: 63-74 - [c122]Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. FCCM 2023: 202 - [c121]Andrew David Gunter, Steve Wilton:
Reformulating the FPGA Routability Prediction Problem with Machine Learning. FCCM 2023: 230-232 - [c120]Andrew David Gunter, Steven J. E. Wilton:
Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. FPGA 2023: 231 - [c119]Esther Roorda, Steven J. E. Wilton:
Online Training from Streaming Data with Concept Drift on FPGAs. ISQED 2023: 1-8 - 2022
- [j45]Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland:
Rethinking Embedded Blocks for Machine Learning Applications. ACM Trans. Reconfigurable Technol. Syst. 15(1): 9:1-9:30 (2022) - [j44]Esther Roorda, Seyedramin Rasoulinezhad, Philip H. W. Leong, Steven J. E. Wilton:
FPGA Architecture Exploration for DNN Acceleration. ACM Trans. Reconfigurable Technol. Syst. 15(3): 33:1-33:37 (2022) - [j43]Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton:
Adaptive Clock Management of HLS-generated Circuits on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(4): 49:1-49:32 (2022) - [c118]Zakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton:
Boosting Domain-Specific Debug Through Inter-frame Compression. FPT 2022: 1-10 - [c117]Jose P. Pinilla, Steven J. E. Wilton:
Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training. SC 2022: 68:1-68:12 - [i5]Nikhil Pratap Ghanathe, Steve Wilton:
T-RECX: Tiny-Resource Efficient Convolutional Neural Networks with Early-Exit. CoRR abs/2207.06613 (2022) - 2021
- [j42]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
In-circuit tuning of deep learning designs. J. Syst. Archit. 118: 102198 (2021) - [c116]Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton:
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM 2021: 20-28 - [c115]Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma, Steve Wilton, Aayan Kumar:
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications. FPL 2021: 347-354 - [i4]Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma, Steve Wilton, Aayan Kumar:
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications. CoRR abs/2107.03653 (2021) - 2020
- [j41]Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton:
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. 13(1): 4:1-4:26 (2020) - [c114]Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton:
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. FPL 2020: 225-230 - [c113]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT 2020: 301
2010 – 2019
- 2019
- [c112]Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA 2019: 110-115 - [c111]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk:
Towards In-Circuit Tuning of Deep Learning Designs. ICCAD 2019: 1-6 - [c110]Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT 2019: 135-143 - [c109]Jose P. Pinilla, Steven J. E. Wilton:
Layout-Aware Embedding for Quantum Annealing Processors. ISC 2019: 121-139 - 2018
- [j40]Fatemeh Eslami, Steven J. E. Wilton:
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. ACM Trans. Design Autom. Electr. Syst. 23(6): 72:1-72:25 (2018) - [j39]Deming Chen, Andrew Putnam, Steven J. E. Wilton:
Introduction to the Special Section on Deep Learning in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 11(3): 14:1-14:3 (2018) - [c108]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS 2018: 1-2 - [c107]Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA 2018: 209-218 - [c106]Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton:
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL 2018: 403-410 - [c105]Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong:
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT 2018: 306-309 - [c104]Daniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton:
LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs. FPT 2018: 393-396 - [c103]Daniel Holanda Noronha, Philip Heng Wai Leong, Steven J. E. Wilton:
Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks. IPDPS Workshops 2018: 178-185 - [i3]Daniel H. Noronha, Bahar Salehpour, Steven J. E. Wilton:
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. CoRR abs/1807.05317 (2018) - 2017
- [j38]Jeffrey Goeders, Steven J. E. Wilton:
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 83-96 (2017) - [c102]Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton:
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL 2017: 1-4 - [c101]Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton:
Rapid circuit-specific inlining tuning for FPGA high-level synthesis. ReConFig 2017: 1-6 - 2016
- [j37]Fatemeh Eslami, Steven J. E. Wilton:
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News 44(4): 20-25 (2016) - [j36]Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk:
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 178-191 (2016) - [c100]Jeffrey Goeders, Steven J. E. Wilton:
Quantifying observability for in-system debug of high-level synthesis circuits. FPL 2016: 1-11 - [c99]Jose P. Pinilla, Steven J. E. Wilton:
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs. FPT 2016: 109-116 - [c98]Marco D. Santambrogio, Ramachandran Vaidyanathan, Diana Goehringer, Steven J. E. Wilton:
RAW Introduction and Committees. IPDPS Workshops 2016: 101-102 - [p1]Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton:
Systems-on-Chip on FPGAs. FPGAs for Software Programmers 2016: 261-283 - [i2]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR abs/1606.06457 (2016) - 2015
- [c97]Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas:
Hierarchical Dynamic Power-Gating in FPGAs. ARC 2015: 27-38 - [c96]Jeffrey B. Goeders, Steven J. E. Wilton:
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. FCCM 2015: 127-134 - [c95]Fatemeh Eslami, Steven J. E. Wilton:
An adaptive virtual overlay for fast trigger insertion for FPGA debug. FPT 2015: 32-39 - [c94]Jeffrey Goeders, Steven J. E. Wilton:
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT 2015: 40-47 - [c93]Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton:
RAW Introduction and Committees. IPDPS Workshops 2015: 68-69 - [i1]Jeffrey B. Goeders, Steven J. E. Wilton:
Allowing Software Developers to Debug HLS Hardware. CoRR abs/1508.06805 (2015) - 2014
- [j35]Assem A. M. Bsoul, Steven J. E. Wilton:
A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices. J. Low Power Electron. 10(1): 1-15 (2014) - [j34]Jeffrey B. Goeders, Steven J. E. Wilton:
Power Aware Architecture Exploration for Field Programmable Gate Arrays. J. Low Power Electron. 10(3): 297-312 (2014) - [j33]Eddie Hung, Steven J. E. Wilton:
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. 19(2): 14:1-14:23 (2014) - [j32]Eddie Hung, Steven J. E. Wilton:
Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 850-863 (2014) - [c92]Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton:
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC 2014: 73-84 - [c91]Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas:
High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. FPL 2014: 1-4 - [c90]Fatemeh Eslami, Steven J. E. Wilton:
Incremental distributed trigger insertion for efficient FPGA debug. FPL 2014: 1-4 - [c89]Jeffrey B. Goeders, Steven J. E. Wilton:
Effective FPGA debug for high-level synthesis generated circuits. FPL 2014: 1-8 - 2013
- [j31]Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton:
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test 30(4): 8-15 (2013) - [j30]Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton:
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs. IEEE Trans. Computers 62(2): 242-246 (2013) - [j29]Joydip Das, Steven J. E. Wilton:
Towards development of an analytical model relating FPGA architecture parameters to routability. ACM Trans. Reconfigurable Technol. Syst. 6(2): 10:1-10:24 (2013) - [j28]Eddie Hung, Steven J. E. Wilton:
Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1103-1115 (2013) - [c88]Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton:
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM 2013: 45-52 - [c87]Eddie Hung, Steven J. E. Wilton:
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA 2013: 19-28 - [c86]Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton:
Maximum flow algorithms for maximum observability during FPGA debug. FPT 2013: 20-27 - 2012
- [j27]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov:
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2(2): 58-70 (2012) - [j26]Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton:
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. ACM Trans. Embed. Comput. Syst. 11(S2): 42:1-42:25 (2012) - [j25]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1295-1303 (2012) - [j24]Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1997-2010 (2012) - [c85]Steven J. E. Wilton, Visvesh S. Sathe:
Advances in 3D design and optimization. CICC 2012: 1 - [c84]Assem A. M. Bsoul, Steven J. E. Wilton:
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA 2012: 245-254 - [c83]Eddie Hung, Steven J. E. Wilton:
Limitations of incremental signal-tracing for FPGA debug. FPL 2012: 49-56 - [c82]Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung:
Rapid RTL-based signal ranking for FPGA prototyping. FPT 2012: 1-7 - [c81]Assem A. M. Bsoul, Steven J. E. Wilton:
An FPGA with power-gated switch blocks. FPT 2012: 87-94 - [c80]Jeffrey B. Goeders, Steven J. E. Wilton:
VersaPower: Power estimation for diverse FPGA architectures. FPT 2012: 229-234 - [c79]Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir:
Emulation in post-silicon validation: It's not just for functionality anymore. HLDVT 2012: 110-117 - 2011
- [j23]Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2195-2208 (2011) - [j22]Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2229-2242 (2011) - [c78]Scott Y. L. Chin, Steven J. E. Wilton:
Towards scalable FPGA CAD through architecture. FPGA 2011: 143-152 - [c77]Joydip Das, Steven J. E. Wilton:
An analytical model relating FPGA architecture parameters to routability. FPGA 2011: 181-184 - [c76]Eddie Hung, Steven J. E. Wilton:
Speculative Debug Insertion for FPGAs. FPL 2011: 524-531 - [c75]Joydip Das, Steven J. E. Wilton:
Accelerated FPGA architecture design: Capabilities and limitations of analytical models. FPT 2011: 1-8 - [c74]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh:
Sequence pair based voltage island floorplanning. IGCC 2011: 1-6 - [c73]Eddie Hung, Steven J. E. Wilton:
On evaluating signal selection algorithms for post-silicon debug. ISQED 2011: 290-296 - [c72]Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton:
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48 - 2010
- [j21]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward:
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 816-829 (2010) - [c71]Steven J. E. Wilton:
Towards Analytical Methods for FPGA Architecture Investigation. ARC 2010: 3 - [c70]Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272 - [c69]Assem A. M. Bsoul, Steven J. E. Wilton:
An FPGA architecture supporting dynamically controlled power gating. FPT 2010: 1-8 - [c68]Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt:
Accelerating trace computation in post-silicon debug. ISQED 2010: 244-249
2000 – 2009
- 2009
- [j20]Scott Y. L. Chin, Steven J. E. Wilton:
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. ACM Trans. Reconfigurable Technol. Syst. 1(4): 18:1-18:20 (2009) - [j19]Bradley R. Quinton, Steven J. E. Wilton:
Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1334-1339 (2009) - [j18]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1709-1718 (2009) - [c67]Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton:
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC 2009: 25-28 - [c66]Alastair M. Smith, Steven J. E. Wilton, Joydip Das:
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA 2009: 181-190 - [c65]Scott Y. L. Chin, Steven J. E. Wilton:
An analytical model relating FPGA architecture and place and route runtime. FPL 2009: 146-153 - [c64]Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
Modeling post-techmapping and post-clustering FPGA circuit depth. FPL 2009: 205-211 - [c63]Scott Y. L. Chin, Steven J. E. Wilton:
Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL 2009: 717-718 - [c62]Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung:
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61 - [c61]Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. FPT 2009: 96-103 - [c60]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward:
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC 2009: 1-4 - [c59]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward:
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC 2009: 357-360 - 2008
- [j17]Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. 2008: 736203:1-736203:10 (2008) - [j16]Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton:
On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfigurable Comput. 2008: 751863:1-751863:13 (2008) - [j15]Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk:
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ACM Trans. Reconfigurable Technol. Syst. 1(1): 7:1-7:25 (2008) - [j14]Julien Lamoureux, Steven J. E. Wilton:
On the trade-off between power and flexibility of FPGA clock networks. ACM Trans. Reconfigurable Technol. Syst. 1(3): 13:1-13:33 (2008) - [j13]Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Practical Asynchronous Interconnect Network Design. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 579-588 (2008) - [j12]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1521-1534 (2008) - [c58]Steven J. E. Wilton, Arif Rahman:
Session 14 - Advanced SoCs - techniques and applications. CICC 2008 - [c57]Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD 2008: 1-10 - [c56]Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226 - [c55]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232 - [c54]Cindy Mark, Ava Shui, Steven J. E. Wilton:
A system-level stochastic circuit generator for FPGA architecture evaluation. FPT 2008: 25-32 - [c53]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing coarse-grained units in floating point hybrid FPGA. FPT 2008: 57-64 - [c52]Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton:
BackSpace: Moving Towards Reality. MTV 2008: 49-54 - [r1]Steven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin, Kara K. W. Poon:
Field-Programmable Gate Array Architectures. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [c51]Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton:
A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41 - [c50]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165 - [c49]Julien Lamoureux, Steven J. E. Wilton:
Clock-Aware Placement for FPGAs. FPL 2007: 124-131 - [c48]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201 - [c47]Bradley R. Quinton, Steven J. E. Wilton:
Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL 2007: 202-209 - [c46]Scott Y. L. Chin, Steven J. E. Wilton:
Memory Footprint Reduction for FPGA Routing Algorithms. FPT 2007: 1-8 - 2006
- [j11]Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov:
System-on-Chip: Reuse and Integration. Proc. IEEE 94(6): 1050-1069 (2006) - [j10]Andy Yan, Steven J. E. Wilton:
Product-Term-Based Synthesizable Embedded Programmable Logic Cores. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 474-488 (2006) - [c45]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo:
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44 - [c44]Julien Lamoureux, Steven J. E. Wilton:
FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108 - [c43]Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton:
Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL 2006: 1-8 - [c42]Julien Lamoureux, Steven J. E. Wilton:
Activity Estimation for Field-Programmable Gate Arrays. FPL 2006: 1-8 - [c41]Julien Lamoureux, Steven J. E. Wilton:
Architecture and CAD for FPGA Clock Networks. FPL 2006: 1-2 - [c40]Nathalie Chan King Choy, Steven J. E. Wilton:
Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. FPT 2006: 253-256 - [e3]Steven J. E. Wilton, André DeHon:
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006. ACM 2006, ISBN 1-59593-292-5 [contents] - 2005
- [j9]Julien Lamoureux, Steven J. E. Wilton:
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electron. 1(2): 119-132 (2005) - [j8]Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova, Resve Saleh:
Design considerations for soft embedded programmable logic cores. IEEE J. Solid State Circuits 40(2): 485-497 (2005) - [j7]Kara K. W. Poon, Steven J. E. Wilton, Andy Yan:
A detailed power model for field-programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 10(2): 279-302 (2005) - [j6]Steven W. Oldridge, Steven J. E. Wilton:
A novel FPGA architecture supporting wide, shallow memories. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 758-762 (2005) - [j5]Peter Hallschmid, Steven J. E. Wilton:
Routing architecture optimizations for high-density embedded programmable IP cores. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1320-1324 (2005) - [c39]Steven J. E. Wilton, Albert Stritter:
Advances in programmable logic. CICC 2005: 168-169 - [c38]Zion S. Kwok, Steven J. E. Wilton:
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. FCCM 2005: 35-44 - [c37]Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180 - [c36]Bradley R. Quinton, Steven J. E. Wilton:
Post-Silicon Debug Using Programmable Logic Cores. FPT 2005: 241-248 - [c35]Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274 - [c34]Bradley R. Quinton, Steven J. E. Wilton:
Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) 2005: 45-48 - [c33]Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton:
Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90 - [e2]Herman Schmit, Steven J. E. Wilton:
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005. ACM 2005, ISBN 1-59593-029-9 [contents] - [e1]Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong:
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. IEEE 2005, ISBN 0-7803-9362-7 [contents] - 2004
- [c32]Andy Yan, Steven J. E. Wilton:
Sequential synthesizable embedded programmable logic cores for system-on-chip. CICC 2004: 435-438 - [c31]Steven J. E. Wilton, Su-Shin Ang, Wayne Luk:
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728 - [c30]Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde:
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT 2004: 33-40 - [c29]Tony Wong, Steven J. E. Wilton:
Placement and routing for non-rectangular embedded programmable logic cores in SoC design. FPT 2004: 65-72 - [c28]Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux:
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) 2004: 885-888 - 2003
- [c27]James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh:
SoC implementation issues for synthesizable embedded programmable logic cores. CICC 2003: 45-48 - [c26]Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton:
Architectures and algorithms for synthesizable embedded programmable logic cores. FPGA 2003: 3-11 - [c25]Steven W. Oldridge, Steven J. E. Wilton:
Placement and routing for FPGA architectures supporting wide shallow memories. FPT 2003: 154-161 - [c24]Andy Yan, Steven J. E. Wilton:
Product-term based synthesizable embedded programmable logic cores. FPT 2003: 162-169 - [c23]Julien Lamoureux, Steven J. E. Wilton:
On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD 2003: 701-708 - 2002
- [c22]Ernie Lin, Steven J. E. Wilton:
The architecture of dual-mode FPGA embedded system blocks. CICC 2002: 67-70 - [c21]Andy Yan, Rebecca Cheng, Steven J. E. Wilton:
On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. FPGA 2002: 147-156 - [c20]Kara K. W. Poon, Andy Yan, Steven J. E. Wilton:
A Flexible Power Model for FPGAs. FPL 2002: 312-321 - [c19]Steven J. E. Wilton:
Implementing logic in FPGA memory arrays: heterogeneous memory architectures. FPT 2002: 142-147 - [c18]Kara K. W. Poon, Steven J. E. Wilton:
Sensitivity of FPGA power evaluation. FPT 2002: 441-442 - 2001
- [j4]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 223-226 (2001) - [c17]Steven J. E. Wilton, Resve Saleh:
Programmable logic IP cores in SoC design: opportunities and challenges. CICC 2001: 63-66 - [c16]Steven W. Oldridge, Steven J. E. Wilton:
A novel FPGA architecture supporting wide shallow memories. CICC 2001: 75-78 - [c15]Steven J. E. Wilton:
A crosstalk-aware timing-driven router for FPGAs. FPGA 2001: 21-28 - [c14]Peter Hallschmid, Steven J. E. Wilton:
Detailed routing architectures for embedded programmable logic IP cores. FPGA 2001: 69-74 - [c13]Ernie Lin, Steven J. E. Wilton:
Macrocell Architectures for Product Term Embedded Memory Arrays. FPL 2001: 48-58 - 2000
- [j3]Steven J. E. Wilton:
Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 56-68 (2000) - [c12]Jason P. Clifford, Steven J. E. Wilton:
Architecture of cluster-based FPGAs with memory. CICC 2000: 131-134 - [c11]Steven J. E. Wilton:
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. FPGA 2000: 67-74 - [c10]Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh:
FPGA Implementation of a Prototype WDM On-Line Scheduler. FPL 2000: 773-776
1990 – 1999
- 1999
- [j2]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 80-91 (1999) - [c9]William K. C. Ho, Steven J. E. Wilton:
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. FPL 1999: 111-123 - [c8]M. Imran Masud, Steven J. E. Wilton:
A New Switch Block for Segmented FPGAs. FPL 1999: 274-281 - 1998
- [c7]Steven J. E. Wilton:
Implementing logic in FPGA embedded memory arrays: architectural implications. CICC 1998: 269-272 - [c6]Steven J. E. Wilton:
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. FPGA 1998: 171-178 - 1997
- [c5]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16 - 1996
- [j1]Steven J. E. Wilton, Norman P. Jouppi:
CACTI: an enhanced cache access and cycle time model. IEEE J. Solid State Circuits 31(5): 677-688 (1996) - 1995
- [c4]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103 - 1994
- [c3]Norman P. Jouppi, Steven J. E. Wilton:
Tradeoffs in Two-Level On-Chip Caching. ISCA 1994: 34-45 - 1993
- [c2]Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton:
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948 - [c1]Steven J. E. Wilton, Zvonko G. Vranesic:
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55
Coauthor Index
Jeffrey B. Goeders
aka: Jeffrey Goeders
aka: Jeffrey Goeders
Philip H. W. Leong
aka: Philip Heng Wai Leong
aka: Philip Heng Wai Leong
Daniel H. Noronha
aka: Daniel Holanda Noronha
aka: Daniel Holanda Noronha
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