"Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits."

Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita (2002)

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DOI: 10.1109/ATS.2002.1181707

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita:
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Asian Test Symposium 2002: 176-181

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