"Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis."

Jason Helge Anderson et al. (2004)

> Home

Details and statistics

DOI: 10.1007/978-3-540-30117-2_19

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/AndersonNCKMC04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/AndersonNCKMC04
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng:
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL 2004: 168-178

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.