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2020 – today
- 2023
[j56]Freddy Forero
, Víctor H. Champac, Michel Renovell:
B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. 19(1): 3:1-3:19 (2023)- [c127]Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli:
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS 2023: 1-6
2010 – 2019
- 2019
- [j55]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. 35(1): 59-75 (2019) - [j54]Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac:
Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2180-2190 (2019) - [c126]Freddy Forero, Michel Renovell, Víctor H. Champac:
B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS 2019: 1-2 - [c125]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS 2019: 1-6 - 2018
- [j53]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34(2): 123-134 (2018) - [c124]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS 2018: 1-5 - 2017
- [j52]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. 33(4): 515-527 (2017) - [c123]Michel Renovell:
Spot defect modeling: Past and evolution. DTIS 2017: 1 - [c122]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS 2017: 1-2 - [c121]Elena-Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras:
Mitigating read & write errors in STT-MRAM memories under DVS. ETS 2017: 1-2 - [c120]Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI 2017: 320-325 - [c119]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Analysis of short defects in FinFET based logic cells. LATS 2017: 1-6 - 2016
- [j51]Jesús Moreno, Michel Renovell, Víctor H. Champac:
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 378-382 (2016) - [c118]Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac:
Behavior and test of open-gate defects in FinFET based cells. ETS 2016: 1-6 - [c117]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI 2016: 164-169 - [c116]Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS 2016: 129-134 - 2015
- [j50]Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Microelectron. J. 46(11): 1091-1102 (2015) - [c115]Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras:
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE 2015: 447-452 - [c114]Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras:
Power-aware voltage tuning for STT-MRAM reliability. ETS 2015: 1-6 - [c113]Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. ISVLSI 2015: 621-626 - [c112]Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard:
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. ISVLSI 2015: 634-639 - 2014
- [j49]Jean-Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell:
Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. 56(4): 173-181 (2014) - [j48]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements. Microelectron. J. 45(3): 336-344 (2014) - [j47]Serge Bernard, Patrick Garda, Michel Renovell:
Editorial. Microelectron. J. 45(10): 1233 (2014) - [j46]Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras:
Sram cell stability metric under transient voltage noise. Microelectron. J. 45(10): 1348-1353 (2014) - [c111]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell:
New implementions of predictive alternate analog/RF test with augmented model redundancy. DATE 2014: 1-4 - [c110]Ioannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale:
DTIS 2014 foreword. DTIS 2014: 1 - [c109]Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos:
Solutions for the self-adaptation of communicating systems in operation. IOLTS 2014: 234-239 - [c108]Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell:
Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. LATW 2014: 1-6 - 2013
- [j45]Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell:
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. 44(9): 840-843 (2013) - [c107]Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian:
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. Asian Test Symposium 2013: 177-182 - [c106]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell:
Implementing model redundancy in predictive alternate test to improve test confidence. ETS 2013: 1 - [c105]Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker:
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. LATW 2013: 1-6 - [c104]Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzerho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti:
Accurate and efficient analytical electrical model of antenna for NFC applications. NEWCAS 2013: 1-4 - 2012
- [c103]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell:
Making predictive analog/RF alternate test strategy independent of training set size. ITC 2012: 1-9 - [c102]Jesús Moreno, Víctor H. Champac, Michel Renovell:
Low voltage testing for interconnect opens under process variations. LATW 2012: 1-6 - [c101]Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma:
Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS 2012: 19-24 - 2011
- [j44]Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell:
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. J. Electron. Test. 27(3): 335-350 (2011) - [c100]Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras:
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium 2011: 413-418 - [c99]Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell:
Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS 2011: 159-162 - [c98]Jesús Moreno, Víctor H. Champac, Michel Renovell:
A new methodology for realistic open defect detection probability evaluation under process variations. VTS 2011: 184-189 - 2010
- [j43]Mohamed Masmoudi, Michel Renovell:
Editorial. Microelectron. J. 41(8): 447-448 (2010) - [c97]Sandra Irobi, Zaid Al-Ars, Michel Renovell:
Parasitic memory effect in CMOS SRAMs. IDT 2010: 134-139
2000 – 2009
- 2009
- [j42]Mariusz Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell:
Functional Testing of Processor Cores in FPGA-Based Applications. Comput. Informatics 28(1): 97-113 (2009) - [j41]Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian:
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4): 56:1-56:21 (2009) - [c96]Florence Azaïs, Yves Bertrand, Michel Renovell:
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163 - [c95]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
A multi-converter DFT technique for complex SIP: Concepts and validation. ECCTD 2009: 747-750 - [c94]Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker:
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26 - 2008
- [j40]Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 327-338 (2008) - [j39]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib:
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design 2008: 482159:1-482159:8 (2008) - [c93]Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker:
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. ETS 2008: 113-118 - [c92]Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell:
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS 2008: 233-238 - [e3]Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová:
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2276-0 [contents] - [e2]Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta:
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. ACM 2008, ISBN 978-1-60558-231-3 [contents] - 2007
- [j38]Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell:
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electron. Test. 23(6): 497-512 (2007) - [j37]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. IET Comput. Digit. Tech. 1(3): 146-153 (2007) - [c91]Florence Azaïs, Laurent Larguier, Michel Renovell:
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits. ATS 2007: 239-244 - [c90]Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker:
SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. ATS 2007: 433-438 - [c89]Philippe Cauvet, Serge Bernard, Michel Renovell:
System-in-Package, a Combination of Challenges and Solutions. ETS 2007: 193-199 - [c88]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS 2007: 211-216 - [c87]Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell:
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI 2007: 192-197 - 2006
- [j36]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Des. Test Comput. 23(3): 234-243 (2006) - [j35]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electron. Test. 22(1): 61-69 (2006) - [j34]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. 22(2): 161-172 (2006) - [j33]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2181-2192 (2006) - [c86]Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker:
Delta-IDDQ Testing of Resistive Short Defects. ATS 2006: 63-68 - [c85]Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker:
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency. ATS 2006: 273-278 - [c84]Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell:
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189 - [c83]Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS 2006: 159-164 - [c82]Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell:
Functional Test of Field Programmable Analog Arrays. VTS 2006: 326-333 - 2005
- [j32]Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell:
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electron. Test. 21(1): 9-16 (2005) - [j31]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. 21(1): 43-55 (2005) - [j30]Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker:
Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electron. Test. 21(1): 57-69 (2005) - [j29]Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electron. Test. 21(2): 135-146 (2005) - [j28]Adoración Rueda, Michel Renovell, José Luis Huertas:
Guest Editorial. J. Electron. Test. 21(3): 203 (2005) - [j27]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. 21(3): 291-298 (2005) - [j26]Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) - [j25]Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell:
Built-in self-test of global interconnects of field programmable analog arrays. Microelectron. J. 36(12): 1112-1123 (2005) - [c81]Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348 - [c80]Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell:
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS 2005: 389-394 - 2004
- [j24]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. 20(3): 257-267 (2004) - [j23]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. 20(4): 375-387 (2004) - [j22]Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell:
A New FPGA for DSP Applications Integrating BIST Capabilities. J. Electron. Test. 20(4): 423-431 (2004) - [c79]Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 - [c78]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88 - [c77]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS 2004: 52-57 - [c76]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Automatic test pattern generation for resistive bridging faults. ETS 2004: 160-165 - [c75]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192 - [c74]David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell:
Scan Design and Secure Chip. IOLTS 2004: 219-226 - [c73]Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski:
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC 2004: 893-902 - [c72]Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure:
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170 - [c71]Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker:
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178 - [c70]Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS 2004: 383-388 - 2003
- [j21]Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. 20(1): 60-67 (2003) - [j20]Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell:
Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Des. Test Comput. 20(2): 32-39 (2003) - [j19]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19(4): 377-386 (2003) - [j18]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. 19(4): 469-479 (2003) - [j17]Michel Renovell:
Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. J. Circuits Syst. Comput. 12(2): 143-158 (2003) - [j16]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. 34(10): 945-953 (2003) - [c69]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 - [c68]Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker:
Modeling feedback bridging faults with non-zero resistance. ETW 2003: 91-96 - [c67]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW 2003: 147-152 - [c66]Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128 - [c65]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209 - [c64]Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059 - 2002
- [j15]Michel Renovell, Florence Azaïs, Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. 19(6): 83-89 (2002) - [c63]Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian:
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301 - [c62]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. ETW 2002: 15-20 - [c61]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW 2002: 89-94 - [c60]Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell:
A New FPGA for DSP Applications Integrating BIST Capabilities. LATW 2002: 76-81 - [c59]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski:
Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW 2002: 174-179 - [c58]Michel Renovell:
A Structural Test Methodology for SRAM-Based FPGAs. SBCCI 2002: 385 - [e1]Manfred Glesner, Peter Zipf, Michel Renovell:
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings. Lecture Notes in Computer Science 2438, Springer 2002, ISBN 3-540-44108-5 [contents] - 2001
- [j14]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. 17(2): 139-147 (2001) - [j13]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. 17(3-4): 255-266 (2001) - [j12]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17(3-4): 283-290 (2001) - [j11]Michel Renovell:
Guest Editorial. J. Electron. Test. 17(5): 371 (2001) - [j10]André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand:
On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 116-128 (2001) - [c57]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595 - [c56]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. DFT 2001: 338-346 - [c55]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 - [c54]Michel Renovell:
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. ISQED 2001: 359-364 - [c53]Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 - [c52]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 - [c51]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW 2001: 112-117 - [c50]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272 - [c49]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271 - 2000
- [j9]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. 16(3): 259-267 (2000) - [j8]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16(3): 289-299 (2000) - [j7]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. 16(5): 513-520 (2000) - [c48]Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83 - [c47]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 - [c46]Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 - [c45]Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell:
Towards an ADC BIST scheme using the histogram test technique. ETW 2000: 53-58 - [c44]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80 - [c43]Michel Renovell:
A Specific Test Methodology for Symmetric SRAM-Based FPGAs. FPL 2000: 300-311 - [c42]Michel Renovell, Yervant Zorian:
Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862 - [c41]Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs:
On the Temperature Dependencies of Analog BIST. LATW 2000: 88-93 - [c40]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW 2000: 118-122 - [c39]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Configuration Generation for FPGA Logic Cells. LATW 2000: 202-208 - [c38]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI 2000: 3-8 - [c37]Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254
1990 – 1999
- 1999
- [j6]Michel Renovell, Florence Azaïs, Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. 14(1-2): 13-22 (1999) - [j5]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. 14(1-2): 159-167 (1999) - [c36]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368 - [c35]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622 - [c34]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Functional and structural testing of switched-current circuits. ETW 1999: 22-27 - [c33]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW 1999: 146-151 - [c32]Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486 - 1998
- [j4]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. 15(1): 45-50 (1998) - [c31]Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell:
Testing for Floating Gates Defects in CMOS Circuits. Asian Test Symposium 1998: 228-236 - [c30]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271 - [c29]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377 - [c28]Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 - [c27]Michel Renovell:
Microsystems Testing: A Challenge. Asian Test Symposium 1998: 512 - [c26]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88 - [c25]Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. DATE 1998: 89-94 - [c24]Michel Renovell, Florence Azaïs, Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821 - [c23]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148 - [c22]Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell:
From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301 - [c21]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111 - [c20]Michel Renovell:
SRAM-based FPGAs: A Structural Test Approach. SBCCI 1998: 67-73 - [c19]Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand:
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI 1998: 175-178 - [c18]Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin:
Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375 - 1997
- [c17]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254- - [c16]Michel Renovell, Florence Azaïs, Yves Bertrand:
On-chip analog output response compaction. ED&TC 1997: 568-572 - [c15]Michel Renovell, Yves Bertrand:
Test Strategy Sensitivity to Defect Parameters. ITC 1997: 607-616 - [c14]Michel Renovell, Joan Figueras, Yervant Zorian:
Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237 - 1996
- [c13]Michel Renovell, P. Huc, Yves Bertrand:
The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC 1996: 205-213 - [c12]Michel Renovell, Florence Azaïs, Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59 - [c11]Michel Renovell, P. Huc, Yves Bertrand:
Bridging fault coverage improvement by power supply control. VTS 1996: 338-343 - 1995
- [j3]Joan Figueras, Michel Renovell:
Current testing in dynamic CMOS circuits. J. Electron. Test. 6(1): 127-131 (1995) - [c10]Michel Renovell, P. Huc, Yves Bertrand:
Serial transistor network modeling for bridging fault simulation. Asian Test Symposium 1995: 100-106 - [c9]Michel Renovell, Florence Azaïs, Yves Bertrand:
A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119 - [c8]S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault:
Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168 - [c7]Michel Renovell, P. Huc, Yves Bertrand:
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS 1995: 184-189 - 1994
- [c6]Michel Renovell, P. Huc, Yves Bertrand:
The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC 1994: 165-177 - [c5]Michel Renovell, P. Huc, Yves Bertrand:
CMOS bridging fault modeling. VTS 1994: 392-397 - 1993
- [c4]Michel Renovell, Joan Figueras:
Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214 - [c3]Yves Bertrand, Frédéric Bancel, Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997 - [c2]Yves Bertrand, Frédéric Bancel, Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54 - 1992
- [j2]Michel Renovell, Gaston Cambon:
Electrical analysis and modeling of floating-gate fault. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1450-1458 (1992) - [c1]Michel Renovell, M. Ildevert, Yves Bertrand:
A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. VLSI Design 1992: 352-353
1980 – 1989
- 1985
- [j1]Michel Renovell, Gaston Cambon, Daniel Auvergne:
FSPICE: a tool for fault modelling in MOS circuits. Integr. 3(3): 245-255 (1985)
Coauthor Index
[j55] [c124] [j52] [c122] [c120] [c117] [c116] [j50] [c113] [c112] [j49] [j48] [c111] [c109] [c108] [j45] [c107] [c106] [c105] [c104] [c103] [c101] [j44] [c96] [c95] [j39] [c92] [j37] [c91] [c88] [j36] [c83] [j32] [j29] [j27] [j26] [j25] [c80] [j24] [j23] [c79] [c73] [c70] [j21] [j20] [j19] [j18] [j16] [c69] [c65] [j15] [c62] [c61] [c59] [j14] [j13] [j10] [c57] [c56] [c55] [c52] [c51] [c50] [c49] [j9] [c48] [c46] [c45] [c41] [c40] [c37] [j6] [c34] [c32] [c29] [c28] [c24] [c19] [c18] [c16] [c12] [c9]
[c96] [c92] [j27] [j26] [j24] [j23] [j21] [j19] [j18] [j16] [c69] [c65] [j15] [c62] [c61] [c59] [j14] [j13] [j10] [c57] [c56] [c55] [c52] [c51] [c50] [c49] [j9] [c48] [c46] [c41] [c40] [c37] [j6] [c34] [c32] [c29] [c28] [c24] [c19] [c18] [c16] [c15] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c3] [c2] [c1]
Jean-Marc Gallière
aka: Jean Marc Gallière
aka: Jean Marc Gallière
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