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2020 – today
- 2024
[c3]Chien-Pang Lu
, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha, Alessandro Uber:
Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization. ISPD 2024: 205-212
2010 – 2019
- 2019
- [j2]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [c2]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40
2000 – 2009
- 2009
- [j1]Chung-Ching Peng, Zhiming Xiao, Rizwan Bashirullah:
Toward Energy Efficient Neural Interfaces. IEEE Trans. Biomed. Eng. 56(11): 2697-2700 (2009) - [c1]Chung-Ching Peng, Pawan Sabharwal, Rizwan Bashirullah:
An Adaptive Neural Spike Detector with Threshold-lock Loop. ISCAS 2009: 2133-2136
Coauthor Index
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