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2020 – today
- 2024
[j30]Shanshan Xie
, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters. IEEE J. Solid State Circuits 59(6): 1950-1961 (2024)- [j29]Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni:
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks. ACM Trans. Archit. Code Optim. 21(2): 39 (2024) - [c59]Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni:
CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems. CICC 2024: 1-2 - [c58]Juhan Ahn, Saroj Satapathy, Jaydeep P. Kulkarni:
Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers. DRC 2024: 1-2 - [c57]Saikat Chakraborty, Jaydeep P. Kulkarni:
Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications. DRC 2024: 1-2 - [c56]Sumanth N. Karanth, Sirish Oruganti, Meizhi Wang, Jaydeep P. Kulkarni:
Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks. HOST 2024: 282-292 - [c55]Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni:
SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture. HPCA 2024: 719-731 - [c54]Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni:
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits. ISSCC 2024: 308-310 - [c53]Yipeng Wang, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni:
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing. ISSCC 2024: 492-494 - 2023
- [j28]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58(5): 1450-1461 (2023) - [j27]Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni:
A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits 58(7): 2109-2124 (2023) - [j26]Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John:
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. ACM Trans. Reconfigurable Technol. Syst. 16(3): 50:1-50:34 (2023) - [c52]Yipeng Wang, Shanshan Xie, Jacob N. Rohan, Meizhi Wang, Mengtian Yang, Sirish Oruganti, Jaydeep P. Kulkarni:
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce. CICC 2023: 1-2 - [c51]S. S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni:
Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges. DAC 2023: 1-4 - [c50]Rishabh Sehgal, Rishab Mehra, Can Ni, Jaydeep P. Kulkarni:
Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines. ESSCIRC 2023: 37-40 - [c49]Yipeng Wang, Mengtian Yang, Shanshan Xie, Meizhi Wang, Jaydeep P. Kulkarni:
CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor. ESSCIRC 2023: 477-480 - [c48]Mengtian Yang, Yipeng Wang, Jaydeep P. Kulkarni:
A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication. HiPC 2023: 61-65 - [c47]Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Yipeng Wang, Meizhi Wang, Sirish Oruganti, Jaydeep P. Kulkarni:
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems. ISSCC 2023: 420-421 - [i3]Naman Maheshwari, Nicholas Malaya, Scott Moe, Jaydeep P. Kulkarni, Sudhanva Gurumurthi:
An Estimator for the Sensitivity to Perturbations of Deep Neural Networks. CoRR abs/2307.12679 (2023) - 2022
- [j25]Tony Tae-Hyoung Kim, Bongjin Kim, Joo-Young Kim, Jaydeep P. Kulkarni:
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 333-337 (2022) - [j24]Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim:
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 338-353 (2022) - [j23]Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
Enabling In-Memory Computations in Non-Volatile SRAM Designs. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 557-568 (2022) - [j22]Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni:
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 57(11): 3453-3465 (2022) - [c46]Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi:
Aging Effects On Clock Gated Memory Phase Paths. DFT 2022: 1-5 - [c45]Saikat Chakraborty, Jaydeep P. Kulkarni:
Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing. DRC 2022: 1-2 - [c44]Saikat Chakraborty, Jaydeep P. Kulkarni:
Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM. DRC 2022: 1-2 - [c43]Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation. DRC 2022: 1-2 - [c42]S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin C. Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, Sanjay Kumar Banerjee:
Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices. DRC 2022: 1-2 - [c41]Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni:
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks. ESSCIRC 2022: 529-532 - [c40]Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep Kulkarni, Lizy K. John:
CoMeFa: Compute-in-Memory Blocks for FPGAs. FCCM 2022: 1-9 - [c39]Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. VLSI Technology and Circuits 2022: 112-113 - [c38]Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni:
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits 2022: 136-137 - [i2]Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep Kulkarni, Lizy K. John:
CoMeFa: Compute-in-Memory Blocks for FPGAs. CoRR abs/2203.12521 (2022) - 2021
- [j21]Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing. IEEE J. Solid State Circuits 56(7): 2205-2220 (2021) - [c37]Rishabh Sehgal, Jaydeep P. Kulkarni:
Trends in Analog and Digital Intensive Compute-in-SRAM Designs. AICAS 2021: 1-4 - [c36]Jacob N. Rohan, Jaydeep P. Kulkarni:
Realizing Direct Convolution in Memory with Systolic-RAM. A-SSCC 2021: 1-3 - [c35]Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni:
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC 2021: 1-2 - [c34]Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni:
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC 2021: 1-2 - [c33]Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni:
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. CICC 2021: 1-2 - [c32]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC 2021: 1-2 - [c31]Kelly Liang, Xiao Wang, Yuchen Zhou, Xin Xu, Calla McCulley, Liang Wang, Jaydeep Kulkarni, Ananth Dodabalapur:
Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors. DRC 2021: 1-2 - [c30]Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni:
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors. ISCAS 2021: 1-5 - [c29]Vishnuvardhan V. Iyer, Meizhi Wang, Jaydeep Kulkarni, Ali E. Yilmaz:
A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations. ISI 2021: 1-6 - [c28]Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. ISSCC 2021: 248-250 - 2020
- [j20]Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni:
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing. IEEE J. Solid State Circuits 55(1): 60-75 (2020) - [j19]Jaydeep P. Kulkarni:
Chip Design 2020. IEEE Micro 40(6): 6-7 (2020) - [j18]Aseem Sayal, Paras Ajay, Mark W. McDermott, S. V. Sreenivasan, Jaydeep P. Kulkarni:
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4760-4776 (2020) - [c27]Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De:
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [i1]Rahul Mathur, Chien-Ju Chao, Rossana Liu, Nikhil Tadepalli, Pranavi Chandupatla, Shawn Hung, Xiaoqing Xu, Saurabh Sinha, Jaydeep Kulkarni:
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology. CoRR abs/2007.16179 (2020)
2010 – 2019
- 2019
- [j17]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [j16]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c26]Jacob N. Rohan, Pingping Zhuang, S. S. Teja Nibhanupudi, Sanjay Kumar Banerjee, Jaydeep P. Kulkarni:
Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices. DRC 2019: 103-104 - [c25]Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing. ISSCC 2019: 228-230 - 2018
- [j15]Jaydeep Kulkarni, Thomas F. Wenisch:
Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design. IEEE Des. Test 35(6): 94-95 (2018) - [j14]Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep Kulkarni:
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing. ACM J. Emerg. Technol. Comput. Syst. 14(1): 8:1-8:17 (2018) - [j13]Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni:
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1919-1928 (2018) - [c24]Subrahmanya Teja, Jaydeep P. Kulkarni:
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation. DAC 2018: 76:1-76:6 - [c23]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [j12]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52(1): 50-63 (2017) - [j11]Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52(1): 229-239 (2017) - [j10]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c22]Jaydeep Kulkarni, Thomas F. Wenisch:
Message from the program co-chairs. ISLPED 2017: 1 - 2016
- [j9]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - [j8]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51(1): 117-129 (2016) - [c21]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC 2016: 152-153 - [c20]John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC 2016: 308-309 - 2015
- [c19]Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni:
A novel slope detection technique for robust STTRAM sensing. ISLPED 2015: 7-12 - [c18]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - [c17]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC 2015: 1-3 - 2014
- [j7]Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 49(4): 917-927 (2014) - [c16]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - 2013
- [c15]Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jiménez:
Improving multi-core performance using mixed-cell cache architecture. HPCA 2013: 119-130 - 2012
- [j6]Jaydeep P. Kulkarni, Kaushik Roy:
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 319-332 (2012) - [c14]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c13]Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 - 2011
- [j5]Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy:
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1727-1730 (2011) - [c12]Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni:
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. NANOARCH 2011: 45-52 - 2010
- [j4]Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy:
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 2-13 (2010) - [j3]Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1838-1847 (2010) - [c11]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c10]Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De:
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC 2010: 1-4 - [c9]Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy:
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. ISSCC 2010: 186-187 - [c8]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [c7]Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy:
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. CICC 2009: 503-506 - [c6]Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta:
Device/circuit interactions at 22nm technology node. DAC 2009: 97-102 - 2008
- [c5]Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
A high sensitivity process variation sensor utilizing sub-threshold operation. CICC 2008: 125-128 - [c4]Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy:
Process variation tolerant SRAM array for ultra low voltage applications. DAC 2008: 108-113 - [c3]Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy:
Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED 2008: 123-128 - 2007
- [j2]Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. IEEE J. Solid State Circuits 42(10): 2303-2313 (2007) - [c2]Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED 2007: 171-176 - [c1]Jaydeep P. Kulkarni, Kaushik Roy:
A High Performance, Scalable Multiplexed Keeper Technique. ISQED 2007: 545-549 - 2004
- [j1]Sameer A. Kibey, Jaydeep P. Kulkarni, Piyush D. Sarode:
A Fast LSF Search Algorithm Based on Interframe Correlation in G.723.1. EURASIP J. Adv. Signal Process. 2004(8): 1107-1112 (2004)
Coauthor Index
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