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2020 – today
- 2024
[j154]Yuan-Pang Huang
, Shen-Iuan Liu:
A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4156-4160 (2024)- [j153]Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu:
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 480-484 (2024) - [j152]Yi-Hao Lan, Shen-Iuan Liu:
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 704-713 (2024) - [j151]Hsi-Kai Peng, Shen-Iuan Liu:
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 787-791 (2024) - [j150]Yi-Hao Lan, Shen-Iuan Liu:
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1263-1272 (2024) - [j149]Jhe-En Lin, Yi-Hao Lan, Shen-Iuan Liu:
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1512-1522 (2024) - 2023
- [j148]Zhi-Heng Kang, Shen-Iuan Liu:
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation. IEEE J. Solid State Circuits 58(3): 806-816 (2023) - 2022
- [j147]Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu:
A Wide-Range FD for Referenceless Baud-Rate CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 60-64 (2022) - [j146]Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu:
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 269-273 (2022) - [j145]Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu:
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 894-898 (2022) - [j144]Jia-Rong Chang, Shen-Iuan Liu:
A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2026-2030 (2022) - [j143]Wen-Chi Huang, Shen-Iuan Liu:
A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 4709-4713 (2022) - [j142]Yao-Hung Tsai, Shen-Iuan Liu:
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 905-914 (2022) - [c56]Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu:
An Adaptive Digital PLL Based on BBPFD Transition Probability. VLSI-DAT 2022: 1-4 - [c55]Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu:
An Injection-Locked Clock Multiplier With Injection Strength Calibration. VLSI-DAT 2022: 1-4 - 2021
- [j141]Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu:
A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4566-4575 (2021) - [j140]Shun-Chi Chang, Shen-Iuan Liu:
A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 161-165 (2021) - [j139]Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin:
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 873-877 (2021) - [j138]Ming-Han Chou, Shen-Iuan Liu:
A Type-I PLL With Foreground Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1103-1107 (2021) - [j137]Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu:
A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1837-1841 (2021) - [c54]Guan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu:
An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique. VLSI-DAT 2021: 1-4 - [c53]Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu:
A Digital Phase-Locked Loop With Background Supply Noise Cancellation. VLSI-DAT 2021: 1-4 - 2020
- [j136]Chung-Jen Kuo, Shen-Iuan Liu:
A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 205-209 (2020) - [j135]Guan-Yu Su, Shen-Iuan Liu:
A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2169-2179 (2020) - [j134]Ming-Chia Chang, Shen-Iuan Liu:
An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell. IEEE Trans. Circuits Syst. 67-II(11): 2432-2436 (2020) - [j133]Kuan-Lin Fu, Shen-Iuan Liu:
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1726-1735 (2020) - [j132]Ming-Han Chou, Shen-Iuan Liu:
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2474-2478 (2020) - [c52]Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu:
A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j131]Che-Wei Tien, Shen-Iuan Liu:
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 177-181 (2019) - [j130]Cheng-En Hsieh, Shen-Iuan Liu:
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 501-510 (2019) - [j129]Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu:
An On-Chip Relaxation Oscillator With Comparator Delay Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 969-973 (2019) - [j128]Yi-An Chang, Shen-Iuan Liu:
A 13.4-MHz Relaxation Oscillator With Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1725-1729 (2019) - [j127]Yu-Kai Chiu, Shen-Iuan Liu:
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2698-2702 (2019) - [c51]Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu:
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time. A-SSCC 2019: 95-98 - 2018
- [j126]Che-Wei Tien, Shen-Iuan Liu:
A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1830-1839 (2018) - [c50]Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu:
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control. A-SSCC 2018: 39-42 - [c49]San-Liang Lee, Jyehong Chen, Shen-Iuan Liu, Chang-Fa Yang, Hen-Wai Tsao, Shih-Hsiang Hsu, Chien-Chung Lin, Chun-Liang Yang, Zhong Jie Zhang, Kuan-Lin Fu, Lung Wei Chung, Tomas Pankra:
Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect. WOCC 2018: 1-4 - 2017
- [j125]Ye-Sing Luo, Shen-Iuan Liu:
A Voltage Multiplier With Adaptive Threshold Voltage Compensation. IEEE J. Solid State Circuits 52(8): 2208-2214 (2017) - [j124]Yen-Hsiang Tseng, Che-Wei Yeh, Shen-Iuan Liu:
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 811-822 (2017) - [j123]Wun-Jian Su, Shen-Iuan Liu:
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 959-968 (2017) - [j122]Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu:
A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 645-649 (2017) - [j121]Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu:
A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1282-1286 (2017) - [c48]Kuan-Lin Fu, Shen-Iuan Liu:
A 56Gbps PAM-4 optical receiver front-end. A-SSCC 2017: 77-80 - 2016
- [j120]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51(2): 412-427 (2016) - [j119]Ting-Kuei Kuan, Shen-Iuan Liu:
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. IEEE J. Solid State Circuits 51(4): 821-831 (2016) - [j118]Liang-Jen Chen, Shen-Iuan Liu:
A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 126-130 (2016) - [j117]Chih-Lu Wei, Shen-Iuan Liu:
A Digital PLL Using Oversampling Delta-Sigma TDC. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 633-637 (2016) - [j116]Liang-Jen Chen, Shen-Iuan Liu:
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1470-1483 (2016) - [c47]Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu:
A digital MDLL using switched biasing technique to reduce low-frequency phase noise. A-SSCC 2016: 101-104 - [c46]Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu:
19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation. ISSCC 2016: 332-333 - 2015
- [j115]Chih-Lu Wei, Ting-Kuei Kuan, Shen-Iuan Liu:
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 548-552 (2015) - [j114]Ting-Kuei Kuan, Shen-Iuan Liu:
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1873-1882 (2015) - [j113]Kai-Hui Zeng, Ting-Kuei Kuan, Shen-Iuan Liu:
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1033-1037 (2015) - [c45]Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with bandwidth calibration. A-SSCC 2015: 1-4 - [c44]Ting-Kuei Kuan, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction. VLSIC 2015: 138- - 2014
- [j112]I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu:
An All-Digital Despreading Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 16-20 (2014) - [j111]Yu-Hsuan Chiang, Shen-Iuan Liu:
Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 661-665 (2014) - [j110]Yu-Hsun Chien, Kuan-Lin Fu, Shen-Iuan Liu:
A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 845-849 (2014) - [c43]Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu:
A 0.43pJ/bit true random number generator. A-SSCC 2014: 33-36 - [c42]Ye-Sing Luo, Shen-Iuan Liu:
A low-input-swing AC-DC voltage multiplier using Schottky diodes. A-SSCC 2014: 245-248 - [c41]Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu:
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting. A-SSCC 2014: 273-276 - [c40]Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu:
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. A-SSCC 2014: 281-284 - [c39]Cheng-En Hsieh, Shen-Iuan Liu:
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS. A-SSCC 2014: 325-328 - [c38]Shih-Hsiang Shen, Chung-Yi Ting, Chi-Yun Liu, Hua Cheng, Shen-Iuan Liu, Chih-Ting Lin:
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis. BHI 2014: 660-663 - 2013
- [j109]Shih-Yuan Kao, Shen-Iuan Liu:
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection. IEEE J. Solid State Circuits 48(2): 391-404 (2013) - [j108]Pin-Hao Feng, Shen-Iuan Liu:
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS. IEEE J. Solid State Circuits 48(2): 405-416 (2013) - [j107]Yi-Chieh Huang, Shen-Iuan Liu:
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing. IEEE J. Solid State Circuits 48(2): 417-428 (2013) - [j106]Shih-Yuan Kao, Shen-Iuan Liu:
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection. IEEE J. Solid State Circuits 48(11): 2815-2826 (2013) - [j105]Yan-Yu Lin, Shen-Iuan Liu:
4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 252-256 (2013) - [j104]I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu:
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 547-551 (2013) - [j103]Yan-Yu Lin, Shen-Iuan Liu:
4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 622-626 (2013) - [j102]I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu:
An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2813-2822 (2013) - [j101]Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu:
Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 827-831 (2013) - [j100]Yu-Hsuan Chiang, Shen-Iuan Liu:
A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 837-841 (2013) - [j99]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 250-258 (2013) - [c37]I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh:
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC 2013: 414-415 - [c36]Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu:
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling. VLSI-DAT 2013: 1-4 - 2012
- [j98]Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee:
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 47(11): 2551-2553 (2012) - [j97]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology. IEEE J. Solid State Circuits 47(11): 2693-2700 (2012) - [j96]Ke-Hou Chen, Shen-Iuan Liu:
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 305-314 (2012) - [j95]I-Ting Lee, Shen-Iuan Liu:
G-Band Injection-Locked Frequency Dividers Using π-type LC Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 315-323 (2012) - [j94]Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu:
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 148-152 (2012) - [j93]I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu:
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 267-271 (2012) - [j92]Kun-Hung Tsai, Shen-Iuan Liu:
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 80-88 (2012) - [c35]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. ISSCC 2012: 244-246 - [c34]Yi-Chieh Huang, Shen-Iuan Liu:
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. ISSCC 2012: 338-340 - [c33]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A fast-locking phase-locked loop using CP control and gated VCO. VLSI-DAT 2012: 1-4 - 2011
- [j91]Bo-Yu Lin, Shen-Iuan Liu:
Analysis and Design of D-Band Injection-Locked Frequency Dividers. IEEE J. Solid State Circuits 46(6): 1250-1264 (2011) - [j90]Chao-Ching Hung, Shen-Iuan Liu:
A Noise Filtering Technique for Fractional-N Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 139-143 (2011) - [j89]Chao-Ching Hung, Shen-Iuan Liu:
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 58-II(6): 321-325 (2011) - [j88]Chang-Lin Hsieh, Shen-Iuan Liu:
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 487-491 (2011) - [j87]Wei-Jen Huang, Shigeisa Nagayasu, Shen-Iuan Liu:
A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8): 1761-1772 (2011) - [j86]Bo-Yu Lin, Shen-Iuan Liu:
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 617-621 (2011) - [j85]Chang-Lin Hsieh, Shen-Iuan Liu:
Decision Feedback Equalizers Using the Back-Gate Feedback Technique. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 897-901 (2011) - [j84]Shih-Yuan Kao, Shen-Iuan Liu:
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 592-602 (2011) - [c32]I-Ting Lee, Chiao-Hsing Wang, Shen-Iuan Liu:
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS. A-SSCC 2011: 93-96 - [c31]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A leakage-current-recycling phase-locked loop in 65nm CMOS technology. A-SSCC 2011: 137-140 - [c30]Yi-Chieh Huang, Shen-Iuan Liu:
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. ISSCC 2011: 356-358 - [c29]Yu-Ming Ying, Shen-Iuan Liu:
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. ISSCC 2011: 444-446 - 2010
- [j83]Jian-Hao Lu, Shen-Iuan Liu:
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. IEEE J. Solid State Circuits 45(2): 433-446 (2010) - [j82]Mu-Chen Huang, Shen-Iuan Liu:
A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 11-15 (2010) - [j81]Shih-Yuan Kao, Shen-Iuan Liu:
A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 178-182 (2010) - [j80]Shih-Yuan Kao, Shen-Iuan Liu:
A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 319-323 (2010) - [j79]Jung-Yu Chang, Shen-Iuan Liu:
A Phase-Locked Loop With Background Leakage Current Compensation. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 666-670 (2010)
2000 – 2009
- 2009
- [j78]Jung-Yu Chang, Shen-Iuan Liu:
A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS. IET Circuits Devices Syst. 3(6): 350-358 (2009) - [j77]Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu:
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. IEEE J. Solid State Circuits 44(3): 775-783 (2009) - [j76]Sheng-You Lin, Shen-Iuan Liu:
A 1.5 GHz All-Digital Spread-Spectrum Clock Generator. IEEE J. Solid State Circuits 44(11): 3111-3119 (2009) - [j75]Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 97-101 (2009) - [j74]Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu:
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 107-111 (2009) - [j73]Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 142-146 (2009) - [j72]Mu-Chen Huang, Shen-Iuan Liu:
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 369-373 (2009) - [j71]Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology". IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 519 (2009) - [j70]Chao-Ching Hung, Shen-Iuan Liu:
A Leakage-Compensated PLL in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 525-529 (2009) - [j69]I-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu:
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 545-549 (2009) - [j68]I-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu:
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 555-559 (2009) - [j67]Jian-Hao Lu, Shen-Iuan Liu:
A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(10): 783-787 (2009) - [j66]Chi-Nan Chuang, Shen-Iuan Liu:
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 850-854 (2009) - [c28]Hwei-Yu Lee, Shen-Iuan Liu:
A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage. ISCAS 2009: 976-979 - [c27]Kun-Hung Tsai, Shen-Iuan Liu:
A 43.7mW 96GHz PLL in 65nm CMOS. ISSCC 2009: 276-277 - [c26]Bo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu:
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS. ISSCC 2009: 282-283 - [c25]Chao-Ching Hung, Shen-Iuan Liu:
A leakage-suppression technique for phase-locked systems in 65nm CMOS. ISSCC 2009: 400-401 - 2008
- [j65]Wei-Jen Huang, Shen-Iuan Liu:
Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array. IET Circuits Devices Syst. 2(3): 306-316 (2008) - [j64]Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu:
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. IEEE J. Solid State Circuits 43(2): 390-398 (2008) - [j63]Chih-Fan Liao, Shen-Iuan Liu:
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS. IEEE J. Solid State Circuits 43(3): 642-655 (2008) - [j62]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. IEEE J. Solid State Circuits 43(5): 1217-1226 (2008) - [j61]Chao-Chyun Chen, Shen-Iuan Liu:
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. IEEE J. Solid State Circuits 43(11): 2413-2421 (2008) - [j60]Chih-Fan Liao, Shen-Iuan Liu:
A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery. IEEE J. Solid State Circuits 43(11): 2492-2502 (2008) - [j59]Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(12): 2587-2591 (2008) - [j58]Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu:
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1): 361-369 (2008) - [j57]I-Hsin Wang, Shen-Iuan Liu:
A 0.18-muhbox m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 136-140 (2008) - [j56]Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 404-408 (2008) - [j55]Che-Fu Liang, Hong-Lin Chu, Shen-Iuan Liu:
10-Gb/s Inductorless CDRs With Digital Frequency Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2514-2524 (2008) - [j54]Shao-Ku Kao, Shen-Iuan Liu:
A Delay-Locked Loop With Statistical Background Calibration. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 961-965 (2008) - [j53]Chi-Nan Chuang, Shen-Iuan Liu:
A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1094-1098 (2008) - [j52]Shao-Hung Lin, Shen-Iuan Liu:
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs. IEEE Trans. Circuits Syst. II Express Briefs 55-II(12): 1214-1218 (2008) - [c24]Chih-Fan Liao, Shen-Iuan Liu:
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR. ISSCC 2008: 100-101 - [c23]Che-Fu Liang, Shen-Iuan Liu:
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells. ISSCC 2008: 224-225 - [c22]Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. ISSCC 2008: 466-467 - 2007
- [j51]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A Multi-Band Burst-Mode Clock and Data Recovery Circuit. IEICE Trans. Electron. 90-C(4): 802-810 (2007) - [j50]Chih-Fan Liao, Shen-Iuan Liu:
A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers. IEEE J. Solid State Circuits 42(2): 329-339 (2007) - [j49]Rong-Jyi Yang, Shen-Iuan Liu:
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. IEEE J. Solid State Circuits 42(2): 361-373 (2007) - [j48]Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. IEEE J. Solid State Circuits 42(6): 1261-1270 (2007) - [j47]Rong-Jyi Yang, Shen-Iuan Liu:
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 42(11): 2338-2347 (2007) - [j46]Sung-Rung Han, Chi-Nan Chuang, Shen-Iuan Liu:
A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 34-37 (2007) - [j45]Ke-Hou Chen, Jian-Hao Lu, Bo-Jiun Chen, Shen-Iuan Liu:
An Ultra-Wide-Band 0.4-10-GHz LNA in 0.18-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 217-221 (2007) - [j44]Shao-Ku Kao, Bo-Jiun Chen, Shen-Iuan Liu:
A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 566-570 (2007) - [j43]Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu:
Spur-Suppression Techniques for Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 653-657 (2007) - [j42]Chi-Nan Chuang, Shen-Iuan Liu:
A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 939-943 (2007) - [j41]Ding-Shiuan Shen, Shen-Iuan Liu:
A Low-Jitter Spread Spectrum Clock Generator Using FDMP. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 979-983 (2007) - [j40]Chao-Chyun Chen, Jung-Yu Chang, Shen-Iuan Liu:
A DLL-Based Variable-Phase Clock Buffer. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1072-1076 (2007) - [c21]Ke-Hou Chen, Jian-Hao Lu, Shen-Iuan Liu:
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry. CICC 2007: 555-558 - [c20]Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. ISSCC 2007: 48-586 - [c19]Chih-Fan Liao, Shen-Iuan Liu:
A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS. ISSCC 2007: 54-586 - [c18]Chi-Nan Chuang, Shen-Iuan Liu:
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology. ISSCC 2007: 178-595 - [c17]Chihun Lee, Shen-Iuan Liu:
A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS. ISSCC 2007: 196-596 - [c16]Hwei-Yu Lee, Shen-Iuan Liu:
A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology. SoCC 2007: 3-6 - [c15]Hwei-Yu Lee, I-Hsin Wang, Shen-Iuan Liu:
A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. SoCC 2007: 11-14 - 2006
- [j39]Chi-Nan Chuang, Shen-Iuan Liu:
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology. IEICE Trans. Electron. 89-C(3): 295-299 (2006) - [j38]Shao-Ku Kao, Shen-Iuan Liu:
All-Digital Clock Deskew Buffer with Variable Duty Cycles. IEICE Trans. Electron. 89-C(6): 753-760 (2006) - [j37]Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu:
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J. Solid State Circuits 41(5): 1051-1061 (2006) - [j36]You-Jen Wang, Shao-Ku Kao, Shen-Iuan Liu:
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles. IEEE J. Solid State Circuits 41(6): 1262-1274 (2006) - [j35]Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu:
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. IEEE J. Solid State Circuits 41(6): 1380-1390 (2006) - [j34]Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu:
A Calibrated Pulse Generator for Impulse-Radio UWB Applications. IEEE J. Solid State Circuits 41(11): 2401-2407 (2006) - [j33]Chun-Yi Kuo, Jung-Yu Chang, Shen-Iuan Liu:
A spur-reduction technique for a 5-GHz frequency synthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 526-533 (2006) - [j32]Rong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu:
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(4): 842-847 (2006) - [j31]Shao-Ku Kao, Shen-Iuan Liu:
All-Digital Fast-Locked Synchronous Duty-Cycle Corrector. IEEE Trans. Circuits Syst. II Express Briefs 53-II(12): 1363-1367 (2006) - [c14]Chihun Lee, Lan-chou Cho, Shen-Iuan Liu:
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. CICC 2006: 397-400 - [c13]Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. CICC 2006: 599-602 - [c12]Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma:
A 14-band Frequency Synthesizer for MB-OFDM UWB Application. ISSCC 2006: 428-437 - [c11]Chih-Fan Liao, Shen-Iuan Liu:
A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet. ISSCC 2006: 2092-2101 - 2005
- [j30]Rong-Jyi Yang, Shen-Iuan Liu:
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. IEICE Trans. Electron. 88-C(6): 1248-1252 (2005) - [j29]Rong-Jyi Yang, Shen-Iuan Liu:
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. IEICE Trans. Electron. 88-C(8): 1726-1730 (2005) - [j28]Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, Shen-Iuan Liu:
CMOS wideband amplifiers using multiple inductive-series peaking technique. IEEE J. Solid State Circuits 40(2): 548-552 (2005) - [j27]Hsiang-Hui Chang, Shen-Iuan Liu:
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. IEEE J. Solid State Circuits 40(3): 661-670 (2005) - [j26]Sung-Rung Han, Shen-Iuan Liu:
A single-path pulsewidth control loop with a built-in delay-locked loop. IEEE J. Solid State Circuits 40(5): 1130-1135 (2005) - [j25]Weihsing Liu, Shen-Iuan Liu, Shui-Ken Wei:
CMOS current-mode divider and its applications. IEEE Trans. Circuits Syst. II Express Briefs 52-II(3): 145-148 (2005) - [j24]Chia-Hsin Wu, Chun-Yi Kuo, Shen-Iuan Liu:
Selective metal parallel shunting inductor and its VCO application. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1811-1818 (2005) - [c10]Chih-Fan Liao, Shen-Iuan Liu:
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver. CICC 2005: 161-164 - [c9]Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao:
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. ISCAS (1) 2005: 368-371 - [c8]Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Lin, Shen-Iuan Liu:
A tunable bandpass ΔΣ modulator using double sampling. ISCAS (4) 2005: 3676-3679 - 2004
- [j23]Sung-Rung Han, Shen-Iuan Liu:
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle. IEEE J. Solid State Circuits 39(3): 463-468 (2004) - [j22]Ming-Huang Liu, Kuo-Chan Huang, Wei-Yang Ou, Tsung-Yi Su, Shen-Iuan Liu:
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC. IEEE J. Solid State Circuits 39(5): 834-836 (2004) - [j21]Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu:
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. IEEE J. Solid State Circuits 39(8): 1356-1360 (2004) - [j20]Chien-Hung Kuo, Shen-Iuan Liu:
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps. IEEE J. Solid State Circuits 39(11): 2041-2045 (2004) - [j19]Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu:
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2356-2364 (2004) - [c7]Chia-Hsin Wu, Jieh-Wei Liao, Shen-Iuan Liu:
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors. ISCAS (1) 2004: 1044-1047 - 2003
- [j18]Weihsing Liu, Shen-Iuan Liu:
CMOS Tunable 1/x Circuit and Its Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(7): 1896-1899 (2003) - [j17]Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A fast locking and low jitter delay-locked loop using DHDL. IEEE J. Solid State Circuits 38(2): 343-346 (2003) - [j16]Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu:
A spread-spectrum clock generator with triangular modulation. IEEE J. Solid State Circuits 38(4): 673-676 (2003) - [j15]Chia-Hsin Wu, Chih-Chun Tang, Shen-Iuan Liu:
Analysis of on-chip spiral inductors using the distributed capacitance model. IEEE J. Solid State Circuits 38(6): 1040-1044 (2003) - [c6]Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu:
A shifted-averaging VCO with precise multiphase outputs and low jitter operation. ESSCIRC 2003: 647-650 - 2002
- [j14]Chih-Chun Tang, Chia-Hsin Wu, Shen-Iuan Liu:
Miniature 3-D inductors in standard CMOS process. IEEE J. Solid State Circuits 37(4): 471-480 (2002) - [j13]Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37(8): 1021-1027 (2002) - [c5]Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. CICC 2002: 49-52 - [c4]Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu:
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. ISCAS (3) 2002: 77-80 - 2001
- [j12]Ming-Huang Liu, Shen-Iuan Liu:
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique. IEEE J. Solid State Circuits 36(1): 122-128 (2001) - [j11]Ching-Yuan Yang, Shen-Iuan Liu:
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. IEEE J. Solid State Circuits 36(2): 266-272 (2001) - [j10]Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu:
A fast-lock mixed-mode DLL using a 2-b SAR algorithm. IEEE J. Solid State Circuits 36(10): 1464-1471 (2001) - [j9]Wei-Hung Chen, Guang-Kaai Dehang, Jong-Woei Chen, Shen-Iuan Liu:
A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme. IEEE J. Solid State Circuits 36(10): 1498-1505 (2001) - [j8]Chien-Hung Kuo, Shr-Lung Chen, Lee-An Ho, Shen-Iuan Liu:
CMOS oversampling ΔΣ magnetic-to-digital converters. IEEE J. Solid State Circuits 36(10): 1582-1586 (2001) - [c3]Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu:
A fast-lock mixed-mode DLL using a 2-b SAR algorithm. CICC 2001: 489-492 - [c2]Lee-An Ho, Shr-Lung Chen, Chien-Hung Kuo, Shen-Iuan Liu:
CMOS oversampling Sigma-Delta magnetic to digital converters. ISCAS (1) 2001: 388-391 - 2000
- [j7]Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tsai, Jingshown Wu:
A double-sampling pseudo-two-path bandpass ΔΣ modulator. IEEE J. Solid State Circuits 35(2): 276-280 (2000) - [j6]Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu:
Clock-deskew buffer using a SAR-controlled delay-locked loop. IEEE J. Solid State Circuits 35(8): 1128-1136 (2000) - [j5]Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, Shen-Iuan Liu:
A 900-MHz 1-V CMOS frequency synthesizer. IEEE J. Solid State Circuits 35(8): 1211-1214 (2000) - [j4]Ching-Yuan Yang, Shen-Iuan Liu:
Fast-switching frequency synthesizer with a discriminator-aided phase detector. IEEE J. Solid State Circuits 35(10): 1445-1452 (2000)
1990 – 1999
- 1999
- [j3]Shen-Iuan Liu, Jiunn-Hwa Lee, Hen-Wai Tsao:
Low-power clock-deskew buffer for high-speed digital circuits. IEEE J. Solid State Circuits 34(4): 554-558 (1999) - [c1]Poki Chen, Shen-Iuan Liu:
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution. CICC 1999: 605-608 - 1998
- [j2]Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu:
New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid State Circuits 33(10): 1568-1571 (1998) - 1994
- [j1]Shen-Iuan Liu, Yuh-Shyan Hwang:
CMOS four-quadrant multiplier using bias feedback techniques. IEEE J. Solid State Circuits 29(6): 750-752 (1994)
Coauthor Index
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