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ORCIDJosé T. de Sousa
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2020 – today
- 2024
[c28]José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias:
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH 2024: 139-146- 2023
- [j14]Mário P. Véstias
, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16(1): 13:1-13:36 (2023) - 2022
- [j13]David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15: 3600-3611 (2022) - 2021
- [j12]Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9: 75864-75877 (2021) - [j11]João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa:
IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms 14(8): 218 (2021) - [j10]Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
Configurable Hardware Core for IoT Object Detection. Future Internet 13(11): 280 (2021) - 2020
- [j9]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8: 107229-107243 (2020) - [j8]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Moving Deep Learning to the Edge. Algorithms 13(5): 125 (2020) - [j7]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77: 103136 (2020) - [c27]Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa:
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC 2020: 288-297
2010 – 2019
- 2019
- [c26]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL 2019: 350-353 - [c25]Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa:
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS 2019: 1-5 - 2018
- [c24]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL 2018: 399-402 - 2017
- [c23]João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
K-means clustering on CGRA. FPL 2017: 1-4 - [c22]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Parallel dot-products for deep learning on FPGA. FPL 2017: 1-4 - 2016
- [c21]João D. Lopes, José T. de Sousa:
Versat, a Minimal Coarse-Grain Reconfigurable Array. VECPAR 2016: 174-187 - 2015
- [c20]Marco Silva Pereira, João Caldinhas Vaz, Carlos Azeredo Leme, José T. de Sousa, João Costa Freire:
An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. ISCAS 2015: 1226-1229
2000 – 2009
- 2008
- [j6]Romanelli Lodron Zuim, José T. de Sousa, Claudionor Coelho:
Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction. IET Comput. Digit. Tech. 2(1): 30-39 (2008) - 2006
- [c19]Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.:
A fast SAT solver algorithm best suited to reconfigurable hardware. SBCCI 2006: 131-136 - [c18]Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.:
A Fast SAT Solver Strategy Based on Negated Clauses. VLSI-SoC 2006: 110-115 - 2005
- [j5]Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva:
Heuristic-Based Backtracking Relaxation for Propositional Satisfiability. J. Autom. Reason. 35(1-3): 3-24 (2005) - [c17]Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves:
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. FPL 2005: 481-486 - 2004
- [j4]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa:
Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004) - [c16]Carlos J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa:
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. FPL 2004: 344-353 - 2003
- [c15]Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva:
Heuristic-Based Backtracking for Propositional Satisfiability. EPIA 2003: 116-130 - [c14]Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa:
Fault Simulation Using Partially Reconfigurable Hardware. FPL 2003: 839-848 - [c13]Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva:
Heuristic Backtracking Algorithms for SAT. MTV 2003: 69-74 - [e1]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa:
Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science 2778, Springer 2003, ISBN 3-540-40822-3 [contents] - 2002
- [c12]N. A. Reis, José T. de Sousa:
On Implementing a Configware/Software SAT Solver. FCCM 2002: 282-283 - [c11]José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura:
DARP - A Digital Audio Reconfigurable Processor. FPL 2002: 556-566 - 2001
- [c10]José T. de Sousa, J. M. da Silva, Miron Abramovici:
A Configurable Hardware/Software Approach to SAT Solving. FCCM 2001: 239-248 - 2000
- [j3]Miron Abramovici, José T. de Sousa:
A SAT Solver Using Reconfigurable Hardware and Virtual Logic. J. Autom. Reason. 24(1/2): 5-36 (2000) - [c9]José T. de Sousa, Vishwani D. Agrawal:
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE 2000: 640-644
1990 – 1999
- 1999
- [c8]Miron Abramovici, José T. de Sousa, Daniel G. Saab:
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC 1999: 684-690 - [c7]Miron Abramovici, José T. de Sousa:
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. FCCM 1999: 306-307 - [c6]José T. de Sousa:
On Defect-Level Estimation and the Clustering Effect. VLSI 1999: 257-268 - 1997
- [j2]José T. de Sousa, Peter Y. K. Cheung:
Diagnosis of Boards for Realistic Interconnect Shorts. J. Electron. Test. 11(2): 157-171 (1997) - [c5]José T. de Sousa, Peter Y. K. Cheung:
Improved diagnosis of realistic interconnect shorts. ED&TC 1997: 501-505 - 1996
- [j1]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams:
Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1286-1293 (1996) - [c4]José T. de Sousa, T. Shen, Peter Y. K. Cheung:
Realistic Fault Extraction for Boards. ED&TC 1996: 612 - 1994
- [c3]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams:
Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC 1994: 436-442 - 1992
- [c2]M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Physical DFT for High Coverage of Realistic Faults. ITC 1992: 642-651 - 1991
- [c1]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira:
IC Defects-Based Testability Analysis. ITC 1991: 500-509
Coauthor Index
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