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ORCIDShen-Fu Hsiao
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2020 – today
- 2024
[c58]Shen-Fu Hsiao, Tzu-Hsien Chao, Yen-Che Yuan, Kun-Chih Chen:
Hardware Accelerator for MobileViT Vision Transformer with Reconfigurable Computation. ISCAS 2024: 1-4- [c57]Shen-Fu Hsiao, Hou-Chun Kuo, Yu Kuo, Kun-Chih Chen:
Neural Network Acceleration Using Digit-Plane Computation with Early Termination. ISCAS 2024: 1-4 - 2022
- [j25]Chua-Chin Wang
, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh:
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4860-4871 (2022) - [c56]Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu:
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS 2022: 46-49 - [c55]Shen-Fu Hsiao, Hung-Ching Li, Yu-Che Yen, Po-Chang Li:
Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. ISCAS 2022: 3107-3110 - 2021
- [c54]Shen-Fu Hsiao, Jyun-Liang Chen, Yi Hsu, Xiang-Ting Huang:
Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. ICCE-TW 2021: 1-2 - [c53]Shen-Fu Hsiao, Bo-Ching Tsai:
Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models. ICCE-TW 2021: 1-2 - [c52]Shen-Fu Hsiao, Yu-Che Yen:
Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators. ICCE-TW 2021: 1-2 - [c51]Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu:
Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. ISCAS 2021: 1-4 - [c50]Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen:
Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. ISCAS 2021: 1-4 - 2020
- [j24]Shen-Fu Hsiao, Kun-Chih Chen, Chih-Chien Lin, Hsuan-Jui Chang, Bo-Ching Tsai:
Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 376-387 (2020) - [c49]Shen-Fu Hsiao, Hsuan-Jui Chang:
Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations. ISCAS 2020: 1-4 - [c48]Shen-Fu Hsiao, Chia-Yang Wong, Yu-Chang Chen:
Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation. ISCAS 2020: 1-4 - [c47]Shen-Fu Hsiao, Yu-Hong Chen:
Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c46]Shen-Fu Hsiao, Kuey-Chin Huang, Yu-Hong Chen:
Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks. APCCAS 2019: 182-185 - [c45]Shen-Fu Hsiao, Jing-Fu Zhan, Chih-Chien Lin:
Low-Complexity Deep Neural Networks for Image Object Classification and Detection. APCCAS 2019: 313-316 - [c44]Shen-Fu Hsiao, Pei-Hsuan Wu, Jien-Min Chen, Kun-Chih Chen:
Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse. ISCAS 2019: 1-4 - 2018
- [c43]Shen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang:
Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks. DSD 2018: 22-29 - [c42]Shen-Fu Hsiao, Chen-Yen Tsai:
Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels. DSD 2018: 276-279 - [c41]Shen-Fu Hsiao, Pei-Hsuen Wu:
Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators. GCCE 2018: 735-736 - [c40]Shen-Fu Hsiao, Kun-Chih Chen, Yi-Hau Chen:
Optimization of Lookup Table Size in Table-Bound Design of Function Computation. ISCAS 2018: 1-4 - [c39]Shen-Fu Hsiao, Chih-Hsuan Chang:
Hardware design of disparity computation for stereo vision using guided image filtering. VLSI-DAT 2018: 1-4 - 2017
- [j23]Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang:
Hierarchical Multipartite Function Evaluation. IEEE Trans. Computers 66(1): 89-99 (2017) - [c38]Shen-Fu Hsiao, Tz-Heng Tz-Heng You:
Hardware efficient implementation of histograms of oriented gradients for pedestrian detection. GCCE 2017: 1-2 - 2016
- [c37]Shen-Fu Hsiao, Jun-Mao Chan, Ching-Hui Wang:
Hardware design of histograms of oriented gradients based on local binary pattern and binarization. APCCAS 2016: 433-435 - [c36]Shen-Fu Hsiao, Kuei-Chun Huang:
Low-power dual-precision table-based function evaluation supporting dynamic precision changes. APCCAS 2016: 710-712 - 2015
- [j22]Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher:
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 466-470 (2015) - [c35]Shen-Fu Hsiao, Shang-Yu Li, Kai-Hsiang Tsao:
Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications. DSP 2015: 110-114 - [c34]Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee:
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT 2015: 1-4 - 2014
- [c33]Shen-Fu Hsiao, Jun-Ming Huang, Po-Sheng Wu:
VLSI implementation of belief-propagation-based stereo matching with linear-model message update. APCCAS 2014: 73-76 - [c32]Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu:
Compression of Lookup Table for Piecewise Polynomial Function Evaluation. DSD 2014: 279-284 - [c31]Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen:
Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. DSD 2014: 551-558 - [c30]Shen-Fu Hsiao, Pu-Cheng Wu:
Design of low-leakage multi-port SRAM for register file in graphics processing unit. ISCAS 2014: 2181-2184 - [c29]Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu:
VLSI implementations of stereo matching using Dynamic Programming. VLSI-DAT 2014: 1-4 - 2013
- [j21]Shen-Fu Hsiao, Jun-Hong Zhang Jian, Ming-Chih Chen:
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 287-291 (2013) - [j20]Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen:
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 875-886 (2013) - [c28]Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen:
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. VLSI-DAT 2013: 1-4 - 2012
- [j19]Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen:
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 292-296 (2012) - [c27]Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen:
Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. APCCAS 2012: 408-411 - [c26]Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee:
Low-cost designs of rectangular to polar coordinate converters for digital communication. APCCAS 2012: 511-514 - [c25]Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, Guan-Fu Yeh:
Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling. ISCAS 2012: 608-611 - 2011
- [j18]Hou-Jen Ko, Shen-Fu Hsiao:
Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 304-308 (2011) - [c24]Shen-Fu Hsiao, Cheng-Han Lee, Yen-Chun Cheng, Andrew Lee:
Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures. ACSCC 2011: 2181-2185 - 2010
- [j17]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 21-25 (2010) - [c23]Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen:
Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. APCCAS 2010: 1079-1082 - [c22]Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang:
A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. ISCAS 2010: 4153-4156
2000 – 2009
- 2009
- [j16]Ming-Chih Chen, Shen-Fu Hsiao:
Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3221-3228 (2009) - [c21]Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC 2009: 131-132 - 2008
- [c20]Shen-Fu Hsiao, Yuan-Nan Chang, Tze-Ching Tien, Kun-Chih Chen:
Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation. APCCAS 2008: 522-525 - [c19]Shen-Fu Hsiao, Hsin-Mau Lee, Yen-Chun Cheng, Ming-Yu Tsai:
Efficient designs of flaoting-point CORDIC rotation and vectoring operations. APCCAS 2008: 1422-1425 - [c18]Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin:
An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. ISCAS 2008: 468-471 - [c17]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS 2008: 2022-2025 - 2006
- [j15]Shen-Fu Hsiao, Ming-Chih Chen, Chia-Shin Tu:
Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 615-626 (2006) - [c16]Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai:
An Automatic Cache Generator Based on Content-Addressable Memory. APCCAS 2006: 1313-1316 - [c15]Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen:
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS 2006: 1631-1634 - [c14]Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng:
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. MTDT 2006: 34-42 - 2005
- [j14]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan:
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. 88-D(7): 1464-1471 (2005) - [j13]Tso-Bing Juang, Shen-Fu Hsiao:
Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Briefs 52-II(6): 299-303 (2005) - [j12]Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee:
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1568-1579 (2005) - [c13]Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen:
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) 2005: 2433-2436 - 2004
- [j11]Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang:
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. IEEE Signal Process. Lett. 11(2): 152-155 (2004) - [j10]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai:
Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8): 1515-1524 (2004) - 2003
- [c12]Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang:
Design and implementation of a video-oriented network-interface-card system. ASP-DAC 2003: 559-560 - 2002
- [j9]Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen:
High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic. VLSI Design 15(1): 417-426 (2002) - [c11]Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao:
Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) 2002: 471-474 - 2001
- [j8]Shen-Fu Hsiao, Wei-Ren Shiue:
A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. IEEE Trans. Circuits Syst. Video Technol. 11(11): 1149-1159 (2001) - [j7]Shen-Fu Hsiao, Jian-Ming Tseng:
Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. J. VLSI Signal Process. 28(3): 205-220 (2001) - 2000
- [j6]Shen-Fu Hsiao, Yor-Chin Tai, Kai-Hsiang Chang:
VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking. IEEE Trans. Consumer Electron. 46(3): 628-636 (2000) - [j5]Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme:
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. J. VLSI Signal Process. 25(2): 155-166 (2000) - [c10]Shen-Fu Hsiao, Wei-Ren Shiue:
Low-cost unified architectures for the computation of discrete trigonometric transforms. ICASSP 2000: 3299-3302 - [c9]Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen:
High-performance multiplexer-based logic synthesis using pass-transistor logic. ISCAS 2000: 325-328
1990 – 1999
- 1999
- [j4]Shen-Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng:
A cost-efficient and fully-pipelinable architecture for DCT/IDCT. IEEE Trans. Consumer Electron. 45(3): 515-525 (1999) - [c8]Shen-Fu Hsiao, Wei-Ren Shiue:
A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. ICASSP 1999: 1929-1932 - [c7]Shen-Fu Hsiao, Wei-Ren Shiue:
New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. ICASSP 1999: 3517-3520 - [c6]Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-Lin Wu:
Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. ICECS 1999: 1217-1220 - [c5]Shen-Fu Hsiao:
A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. ISCAS (1) 1999: 455-458 - 1998
- [j3]Shen-Fu Hsiao, Jen-Yin Chen:
Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure. J. VLSI Signal Process. 20(3): 267-278 (1998) - 1997
- [c4]Shen-Fu Hsiao, Chung-Yi Yen:
New unified VLSI architectures for computing DFT and other transforms. ICASSP 1997: 615-618 - 1996
- [j2]Shen-Fu Hsiao, Jean-Marc Delosme:
Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms. IEEE Trans. Signal Process. 44(3): 685-697 (1996) - 1995
- [j1]Shen-Fu Hsiao, Jean-Marc Delosme:
Householder CORDIC Algorithms. IEEE Trans. Computers 44(8): 990-1001 (1995) - [c3]Shen-Fu Hsiao:
Adaptive Jacobi method for parallel singular value decompositions. ICASSP 1995: 3203-3206 - 1994
- [c2]Shen-Fu Hsiao, Jean-Marc Delosme:
Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms. ASAP 1994: 324-335 - 1991
- [c1]Shen-Fu Hsiao, Jean-Marc Delosme:
The CORDIC Householder algorithm. IEEE Symposium on Computer Arithmetic 1991: 256-263
Coauthor Index
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