Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40nm DRAM Device

Soo Han CHOI; Young Hee PARK; Chul Hong PARK; Sang Hoon LEE; Moon Hyun YOO; Jun Dong CHO; Gyu Tae KIM

doi:10.1587/transele.E93.C.658

Special Section on Fundamentals and Applications of Advanced Semiconductor Devices

Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40nm DRAM Device

Soo Han CHOI, Young Hee PARK, Chul Hong PARK, Sang Hoon LEE, Moon Hyun YOO, Jun Dong CHO, Gyu Tae KIM

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Keywords: edge effects, analytic model, retargeting, shaping gate channels, OPC, leakage current, drive current

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2010 Volume E93.C Issue 5 Pages 658-661

DOI https://doi.org/10.1587/transele.E93.C.658

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Abstract

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model I_leakage and I_{leakage_fringe} which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

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