Compilation Techniques for Reconfigurable Analog Devices

Abstract

Reconfigurable dynamical-system solving analog devices are a powerful new ultra-low-power computing substrate capable of executing dynamical systems in a performant and energy-efficient manner. This class of devices leverages the physical behavior of transistors to directly implement computation. Under this paradigm, voltages and currents within the device implement continuously evolving variables in the computation. These hardware platforms are challenging to use because they are subject to a variety of low-level physical behaviors that profoundly affect the computation. Relevant physical behaviors include operating range and frequency limitations, noise, process variation, and quantization error.

In this thesis, I present compilation techniques for automatically configuring such devices to execute dynamical systems and present the first compiler that automatically targets a physical dynamical system-solving reconfigurable analog device of this class. The presented compiler frees the end user from reasoning about the low-level physical behaviors present in the hardware and automates the process of mapping the dynamical system to the analog hardware. This thesis also introduces specification languages for describing dynamical systems, and the capabilities and physical limitations of the reprogrammable analog hardware. The compiler targets these specifications when mapping the computation.

To faithfully implement a computation, the compiler configures the device so that the original dynamical system dynamics can be recovered from the physics of the device at runtime. The mapped computation simultaneously leverages the device physics to implement the desired computation, respect the physical limitations of the device, and attenuate away the unwanted physical behaviors present in the analog hardware. The compiler configures and composes together the analog blocks and simultaneously accounts for all of the low-level behaviors present in the device.

The compiler first maps the target dynamical system to the analog hardware and then transforms the produced circuit to attenuate away unwanted analog behavior. The compiler employs a multi-stage, algebraic rewrite-based circuit synthesis procedure to map the dynamical system to the analog hardware. This procedure synthesizes analog circuits that effectively use parametric and specialized analog blocks and leverage physical laws to perform computation.

The compiler automatically transforms the mapped circuit to attenuate away the unwanted analog behaviors present in the circuit. This transformation transforms the signals to respect the operating range and frequency limitations present in the hardware and reduces the effect of analog noise, quantization error, process variation-induced behavioral deviations on the computation. The transformed circuit preserves the original dynamics of the system such that the original dynamical system variable trajectories can be recovered by applying a compiler-derived recovery transform. The compiler formulates the problem of transforming the circuit as a convex optimization problem – this enables the compiler to optimally identify circuit transformations that maximize circuit characteristics such as execution speed and signal quality.

The compiler deploys a cross-cutting program optimization in which the calibration algorithm and compiler work together to reduce the effect of process variation-induced behavioral variations on the overall computation. This thesis presents the concept of a delta model, a hardware abstraction that captures the device-specific behavioral deviations present in the calibrated analog hardware.

The compiler uses this hardware abstraction to compensate for behavioral variations for the specific device at hand while transforming the circuit. This optimization involves all parts of the software stack. I introduce delta model language constructs to the hardware specification language, develop a novel delta-model aware circuit scaling optimization, and introduce new calibration and characterization procedures into the device runtime and firmware to implement this optimization. With this optimization enabled, I am able to attain higher fidelity results with more consistency on the target hardware. This thesis also presents a co-designed calibration algorithm that prioritizes eliminating behavioral deviations that cannot be compensated for in compilation.

I evaluate the compiler on applications from the biology, physics, and controls domains. The results demonstrate that these applications execute with acceptable error while consuming microjoules of energy