Jump to content

SSE5

From Wikipedia, the free encyclopedia

The SSE5 (short for Streaming SIMD Extensions version 5) was a SIMD instruction set extension proposed by AMD on August 30, 2007 as a supplement to the 128-bit SSE core instructions in the AMD64 architecture.

AMD chose not to implement SSE5 as originally proposed. In May 2009, AMD replaced SSE5 with three smaller instruction set extensions named as XOP, FMA4, and F16C, which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set.

The three SSE5-derived instruction sets were introduced in the Bulldozer processor core, released in October 2011 on a 32 nm process.[1]

Compatibility

[edit]

AMD's SSE5 extension bundle does not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor.

SSE5 enhancements

[edit]

The proposed SSE5 instruction set consisted of 170 instructions (including 46 base instructions), many of which are designed to improve single-threaded performance. Some SSE5 instructions are 3-operand instructions, the use of which will increase the average number of instructions per cycle achievable by x86 code.[2] Selected new instructions include:[3]

AMD claimed SSE5 would provide dramatic performance improvements, particularly in high-performance computing (HPC), multimedia, and computer security applications, including a 5x performance gain for AES encryption and a 30% performance gain for the discrete cosine transform (DCT) used for example in video processing.[2]

2009 revision

[edit]

The SSE5 specification included a proposed extension to the general coding scheme of x86 instructions in order to allow instructions to have more than two operands. In 2008, Intel announced their planned AVX instruction set which proposed a different way of coding instructions with more than two operands. The two proposed coding schemes, SSE5 and AVX, are mutually incompatible, although the AVX scheme has certain advantages over the SSE5 scheme: most importantly, AVX has plenty of space for future extensions, including larger vector sizes.

In May 2009, AMD published a revised specification for the planned future instructions. This revision changes the coding scheme to make it compatible with the AVX scheme, but with a differing prefix byte in order to avoid overlap between instructions introduced by AMD and instructions introduced by Intel.

The revised instruction set no longer carries the name SSE5, which has been criticized for being misleading, but most of the instructions in the new revision are functionally identical to the original SSE5 specification—only the way the instructions are coded differs. The planned additions to the AMD instruction set consists of three subsets:

  1. XOP: Integer vector multiply–accumulate instructions, integer vector horizontal addition, integer vector compare, shift and rotate instructions, byte permutation and conditional move instructions, floating point fraction extraction.
  2. FMA4: Floating-point vector multiply–accumulate.
  3. F16C: Half-precision floating-point conversion.

Both XOP and FMA4 are removed in newer AMD processors using the Zen microarchitecture.[4]

See also

[edit]

References

[edit]
  1. ^ Hruska, Joel (November 14, 2008). "AMD Fusion now pushed back to 2011". Ars Technica.
  2. ^ a b Vance, Ashlee (August 30, 2007). "AMD plots single thread boost with x86 extensions". The Register.
  3. ^ "128-Bit SSE5 Instruction Set". AMD Developer Central. Archived from the original on January 15, 2008. Retrieved January 28, 2008.
  4. ^ Michael Larabel (March 3, 2017). "The Impact Of GCC Zen Compiler Tuning On AMD Ryzen Performance". Phoronix. But with Zen being a clean-sheet design, there are some instruction set extensions found in Bulldozer processors not found in Zen/znver1. Those no longer present include FMA4 and XOP.
[edit]

Retrieved from "https://en.wikipedia.org/w/index.php?title=SSE5&oldid=1255943841"