http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0766309-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3011 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4824 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-482 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 1996-08-23^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ade02b78720f93eb353a79dcebb0328 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09ab4316d2478d618722642b83341468 |
| publicationDate | 1997-04-02^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0766309-A2 |
| titleOfInvention | Field effect transistor which multi-level metallisation related to integrated circuits |
| abstract | CMOS power device (10) is provided. A tank region (62) is formed in a semiconductor substrate (60). A polysilicon gate layer (34) is disposed above the tank region (62) and defines a plurality of source and drain diffusion openings (38 and 36) having rounded inner corners (40). A plurality of backgate contact regions (42) are segmented and are formed in vacancies in a plurality of source regions (30). Multi-level metallization layers (64 and 66) are disposed above an active device region of the semiconductor substrate (60) and comprise: staggered source contacts (44) and vias (46) alternating along a center line where the source contacts (44) are located above and extend over the backgate contact regions (42), drain contacts (48) and vias (50) alternating along a center line, alternating and offset sets of gate contacts (52) and vias (54) alternating and offset where the sets are offset with respect to adjacent sets, source, drain and gate bussing (14, 16 and 20), and a center gate bus (22) located on a center line of the power device (10) coupled to the gate bussing (20). A plurality of source bond pads (18) and drain bond pads (29) are formed on opposite edges of the power device (10) and are coupled to the source bussing (14) and drain bussing (16), respectively. Thick upper level metallization (24) is disposed above the source bussing (14) and the drain bussing (16) and extends between associated bond pads (18 and 29). |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0818828-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5949106-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03094241-A1 |
| priorityDate | 1995-08-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 31 of 31.