http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3653569-A1

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filingDate 2019-06-28^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4fc0025682c8adb27c90d36fb33f1e1a
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publicationDate 2020-05-20^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-3653569-A1
titleOfInvention Gate-all-around integrated circuit structures having high mobility
abstract Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire (504) or nanoribbon. A gate stack (508, 506) is around the silicon nanowire or nanoribbon, the gate stack including a compressively stressing gate electrode (506). A first N-type epitaxial source or drain structure (514) is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure (516) is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.
priorityDate 2018-09-27^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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