| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_02d99acd0b92156c011c671a259f2295 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-1204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K23-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-12015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-26 |
| filingDate |
2020-03-30^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-04-21^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_64c65987b2a75b64d2954c33f94f5a3d |
| publicationDate |
2021-04-21^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I725799-B |
| titleOfInvention |
Fail bit number counting circuit and non-volatile semiconductor storage device |
| abstract |
A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11513880-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I775638-B |
| priorityDate |
2019-06-12^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |