http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8379451-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b8a3ecf23c10d4e4c0c0510cff9abf5d http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9de2e7a268fa1cc2f8329d4479e36cfc |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50004 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34 |
| filingDate | 2011-09-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-02-19^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_471b159124d5e7543e0b072c3e0c51ba http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79a3a7802b1b171c1cd1cd445631fcaf |
| publicationDate | 2013-02-19^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8379451-B2 |
| titleOfInvention | Semiconductor memory device |
| abstract | According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each of the logical gates outputs a logical level to a next-stage logical gate in the series connection. The logic level indicates presence or absence of verify-failure in the associated column. The counter counts the number of output times of the logic level indicating the presence of the verify-failure in a final-stage logic gate of the series connection. A content indicated by the logic level output from each of the logic gates is inverted at a boundary of the logic gate associated with the column having the verify-failure in the logic gate chain. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I725799-B |
| priorityDate | 2011-03-25^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID132460 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID415829060 |
Showing number of triples: 1 to 23 of 23.