| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6af9a57049d2d91c036d4f5ab49154cb |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 |
| filingDate |
2018-07-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-07-16^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f9ae1525d653b855e269207d10ae1cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e2b7023123d81e0a7b91a3d81649360
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_28d9449fe73726182353762864569745
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c3adcfa54466d9b855b1e8e33da998ea |
| publicationDate |
2019-07-16^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10354928-B2 |
| titleOfInvention |
Integration scheme for gate height control and void free RMG fill |
| abstract |
A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal. |
| priorityDate |
2017-04-21^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |