| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1211 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7856
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-367
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 |
| filingDate |
2019-06-24^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-12-22^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a1f32ff4bbd6a4413125900a88b7f38d |
| publicationDate |
2020-12-22^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10872839-B2 |
| titleOfInvention |
Method for manufacturing semiconductor device |
| abstract |
A method includes doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along a direction; forming a first gate stack across the first semiconductor fin and a second gate stack across the second semiconductor fin; forming a first source/drain adjoining the first semiconductor fin and a second source/drain adjoining the second semiconductor fin; and forming a first contact over the first source/drain and having a first width measured along the direction and a second contact over the second source/drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I804955-B |
| priorityDate |
2018-03-29^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |