http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006249755-A1
Outgoing Links
Predicate | Object |
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e13c1a677431fe55230e64cc481a86f0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3cc27edbd601bdeff542beb4a76b417b |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 |
filingDate | 2005-05-06^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52eb517bf0033f24d7eb216946da9899 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34f3f4e4189d9c984a0bf169728d8dfd |
publicationDate | 2006-11-09^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | US-2006249755-A1 |
titleOfInvention | Method to prevent arcing during deep via plasma etching |
abstract | A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9040333-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008029844-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8772100-B2 |
priorityDate | 2005-05-06^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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