http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020091310-A1

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filingDate 2019-11-25^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_648b7e03d52ce6e763b6d3b7cc55f924
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publicationDate 2020-03-19^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2020091310-A1
titleOfInvention A method and related apparatus for reducing gate-induced drain leakage in semiconductor devices
abstract In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10748891-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020258879-A1
priorityDate 2018-05-30^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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