| abstract |
Switching noise at integrated circuit V DD and V SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V DD -carrying and V SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance ΔX corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance ΔX, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V SS and V DD . These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise. |