| abstract |
A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased. |