| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e0b1dc47dc14ba038c361312f7f8f2b1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f2c7660ec67e6f3463d165443c2663c2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8720d8da2dbbf32f0e6b3b3f4a6785b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8db6c6b6b74873332bb3ebf81cbdddca
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate |
2011-11-17^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-06-18^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b4afc195d82986d17bf4827c6b5a2ef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0cdf1ab859ed8445d174db32cd58f085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ac549c7bb15bdfe2adfcbf4bdf693e0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe25d135668543bd2da789ad81e4b813 |
| publicationDate |
2013-06-18^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8466496-B2 |
| titleOfInvention |
Selective partial gate stack for improved device isolation |
| abstract |
A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10056301-B2 |
| priorityDate |
2011-11-17^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |