http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9773728-B1

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
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filingDate 2016-12-27^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-09-26^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6221a8a10ab8461f761f6aabf01967d1
publicationDate 2017-09-26^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9773728-B1
titleOfInvention Memory arrays
abstract Some embodiments include memory arrays having rows of fins. Each fin includes a first pedestal, a second pedestal and a trench between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trench between the first and second pedestals. The rows are subdivided amongst deep-type (D) rows and shallow-type (S) rows, with the deep-type rows having deeper channel regions than the shallow-type rows. Some embodiments include rows of fins in which the channel regions along individual rows are subdivided amongst deep-type (D) channel regions and shallow-type (S) channel regions, with the deep-type channel regions being below the shallow-type channel regions.
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