| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-405
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-403 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-405
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2015-12-01^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2017-10-03^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_594727610dcd2c320965a69d1fdd291b |
| publicationDate |
2017-10-03^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9779782-B2 |
| titleOfInvention |
Semiconductor device and electronic device |
| abstract |
In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell. |
| priorityDate |
2014-12-08^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |