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Roger Dean Chamberlain
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2020 – today
- 2024
[c129]James H. Buckley
, Jeremy Buhler, Roger D. Chamberlain:
The Advanced Particle-astrophysics Telescope (APT): Computation in Space. CF (Companion) 2024- [c128]Marion Sudvarg, Chenfeng Zhao, Ye Htet, Meagan Konst, Thomas Lang, Nick Song, Roger D. Chamberlain, Jeremy Buhler, James H. Buckley:
HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne Instrument. CF 2024 - [c127]Clayton J. Faber, Roger D. Chamberlain:
Application of Network Calculus Models to Heterogeneous Streaming Applications. IPDPS (Workshops) 2024: 198-201 - 2023
- [c126]Chenfeng Zhao, Roger D. Chamberlain, Xuan Zhang:
SuperCut: Communication-Aware Partitioning for Near-Memory Graph Processing. CF 2023: 42-51 - [c125]Chenfeng Zhao, Zehao Dong, Yixin Chen, Xuan Zhang, Roger D. Chamberlain:
GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis. ICCD 2023: 574-577 - [c124]Marion Sudvarg, Jeremy Buhler, Roger D. Chamberlain, Christopher D. Gill, James H. Buckley, Wenlei Chen:
Parameterized Workload Adaptation for Fork-Join Tasks with Dynamic Workloads and Deadlines. RTCSA 2023: 232-242 - [c123]Ye Htet, Marion Sudvarg, Jeremy Buhler, Roger D. Chamberlain, James H. Buckley:
Localization of Gamma-ray Bursts in a Balloon-Borne Telescope. SC Workshops 2023: 395-398 - [i2]Chenfeng Zhao, Zehao Dong, Yixin Chen, Xuan Zhang, Roger D. Chamberlain:
GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis. CoRR abs/2309.16022 (2023) - 2022
- [j24]Chenfeng Zhao, Xuan Zhang, Roger D. Chamberlain:
Executing Data Integration Effectively and Efficiently Near the Memory. IEEE Des. Test 39(2): 65-73 (2022) - [c122]Tim Bell, Todd Steinbrueck, Roger D. Chamberlain, Brian Rieck:
IoT Benefits for Livestock Farmers. DCOSS 2022: 159-166 - [c121]Clayton J. Faber, Steven D. Harris, Zhili Xiao, Roger D. Chamberlain, Anthony M. Cabrera:
Challenges Designing for FPGAs Using High-Level Synthesis. HPEC 2022: 1-7 - [c120]Roger D. Chamberlain, James Orr, Doug Shook, Bill Siever:
Advancing Your Arduino Game: Early and Engaging Scaffolding for Advanced CS. SIGCSE (2) 2022: 1196 - 2021
- [c119]Zhili Xiao, Roger D. Chamberlain, Anthony M. Cabrera:
HLS Portability from Intel to Xilinx: A Case Study. HPEC 2021: 1-8 - [c118]Anthony M. Cabrera, Aaron R. Young, Jacob Lambert, Zhili Xiao, Amy An, Seyong Lee, Zheming Jin, Jungwon Kim, Jeremy Buhler, Roger D. Chamberlain, Jeffrey S. Vetter:
Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs. IWOCL 2021: 7:1-7:9 - [c117]Bryan Orabutt, Roger D. Chamberlain, Jonathan Elson, George Engel, Franck Delaunay, Lee G. Sobotka:
Design of Mixed-mode Systems for Pulse-shape Discrimination. MWSCAS 2021: 990-994 - [c116]Clayton J. Faber, Tom Plano, Samatha Kodali, Zhili Xiao, Abhishek Dwaraki, Jeremy D. Buhler, Roger D. Chamberlain, Anthony M. Cabrera:
Platform Agnostic Streaming Data Application Performance Models. RSDHA@SC 2021: 17-26 - [c115]Jacob Wheelock, William Kanu, Marion Sudvarg, Zhili Xiao, Jeremy D. Buhler, Roger D. Chamberlain, James H. Buckley:
Supporting Multi-messenger Astrophysics with Fast Gamma-ray Burst Localization. UrgentHPC@SC 2021: 21-28 - 2020
- [j23]Roger D. Chamberlain:
Architecturally truly diverse systems: A review. Future Gener. Comput. Syst. 110: 33-44 (2020) - [c114]Anthony M. Cabrera, Roger D. Chamberlain:
Designing Domain Specific Computing Systems. FCCM 2020: 221 - [c113]Anthony M. Cabrera, Roger D. Chamberlain:
Design and Performance Evaluation of Optimizations for OpenCL FPGA Kernels. HPEC 2020: 1-7 - [c112]Steven D. Harris, Roger D. Chamberlain, Christopher D. Gill:
OpenCL Performance on the Intel Heterogeneous Architecture Research Platform. HPEC 2020: 1-9 - [c111]Darko Ivanovich, Chenfeng Zhao, Xuan Zhang, Roger D. Chamberlain, Amit Deliwala, Viktor Gruev:
Chip-to-chip Optical Data Communications using Polarization Division Multiplexing. HPEC 2020: 1-8 - [c110]Roger D. Chamberlain, Todd Steinbrueck:
Demo Abstract: More Than Two Decades of IoT. IoTDI 2020: 268-269 - [e3]Roger D. Chamberlain, Martin Edin Grimheden, Walid Taha:
Cyber Physical Systems. Model-Based Design - 9th International Workshop, CyPhy 2019, and 15th International Workshop, WESE 2019, New York City, NY, USA, October 17-18, 2019, Revised Selected Papers. Lecture Notes in Computer Science 11971, Springer 2020, ISBN 978-3-030-41130-5 [contents]
2010 – 2019
- 2019
- [c109]Tim Bell, Roger D. Chamberlain, Mike Chambers, Brian Rieck, Todd Steinbrueck:
Security on the Farm: Safely Communicating with Legacy Agricultural Instrumentation. DCOSS 2019: 192-194 - [c108]Roger D. Chamberlain, Mike Chambers, Darren Greenwalt, Maria Scharth, Brett Steinbrueck, Todd Steinbrueck, David Thomas:
Water in the Cloud: Understanding Water Chemistry via the Internet of Things. DCOSS 2019: 408-415 - [c107]Anthony M. Cabrera, Roger D. Chamberlain, Jonathan C. Beard:
Multi-spectral Reuse Distance: Divining Spatial Information from Temporal Data. HPEC 2019: 1-8 - [c106]Anthony M. Cabrera, Roger D. Chamberlain:
Exploring Portability and Performance of OpenCL FPGA Kernels on Intel HARPv2. IWOCL 2019: 3:1-3:10 - [c105]Clayton J. Faber, Anthony M. Cabrera, Orondé Booker, Gabe Maayan, Roger D. Chamberlain:
Data Integration Tasks on Heterogeneous Systems Using OpenCL. IWOCL 2019: 19:1 - [c104]Bill Siever, Roger D. Chamberlain, Elliott Forbes, Ingrid Russell:
Including Embedded Systems in CS: Why? When? and How? SIGCSE 2019: 328-329 - [e2]Roger D. Chamberlain, Walid Taha, Martin Törngren:
Cyber Physical Systems. Design, Modeling, and Evaluation - 7th International Workshop, CyPhy 2017, Seoul, South Korea, October 15-20, 2017, Revised Selected Papers. Lecture Notes in Computer Science 11267, Springer 2019, ISBN 978-3-030-17909-0 [contents] - [e1]Roger D. Chamberlain, Walid Taha, Martin Törngren:
Cyber Physical Systems. Model-Based Design - 8th International Workshop, CyPhy 2018, and 14th International Workshop, WESE 2018, Turin, Italy, October 4-5, 2018, Revised Selected Papers. Lecture Notes in Computer Science 11615, Springer 2019, ISBN 978-3-030-23702-8 [contents] - 2018
- [j22]Lin Ma, Roger D. Chamberlain, Kunal Agrawal, Chen Tian, Ziang Hu:
Analysis of classic algorithms on highly-threaded many-core architectures. Future Gener. Comput. Syst. 82: 528-543 (2018) - [c103]Roger D. Chamberlain, Chris Edmiston, Don Williams:
Automated Titration in a Recirculating Water System. CySWATER@CPSWeek 2018: 12-15 - [c102]Roger D. Chamberlain, Ron K. Cytron, Doug Shook, Bill Siever:
Computers Interacting with the Physical World: A First-Year Course. CyPhy/WESE 2018: 197-205 - [c101]Roger D. Chamberlain, Chandler Ahrens, Christopher D. Gill, Scott A. Mitchell:
Hierarchical control of a catoptric surface: work-in-progress. EMSOFT 2018: 7 - [c100]Anthony M. Cabrera, Clayton J. Faber, Kyle Cepeda, Robert Derber, Cooper Epstein, Jason Zheng, Ron K. Cytron, Roger D. Chamberlain:
DIBS: A Data Integration Benchmark Suite. ICPE Companion 2018: 25-28 - 2017
- [j21]Jonathan C. Beard, Peng Li, Roger D. Chamberlain:
RaftLib: A C++ template library for high performance stream parallel processing. Int. J. High Perform. Comput. Appl. 31(5): 391-404 (2017) - [c99]Roger D. Chamberlain, Mike Chambers, Darren Greenwalt, Brett Steinbrueck, Todd Steinbrueck:
Water in the Cloud: Remote Understanding of Water Chemistry: Poster Abstract. IoTDI 2017: 353-354 - [c98]Roger D. Chamberlain:
Assessing user preferences in programming language design. Onward! 2017: 18-29 - 2016
- [c97]Roger D. Chamberlain, Mike Chambers, Darren Greenwalt, Brett Steinbrueck, Todd Steinbrueck:
Layered Security and Ease of Installation for Devices on the Internet of Things. IoTDI 2016: 297-300 - [c96]John Meier, Christopher D. Gill, Roger D. Chamberlain:
Combining Admission and Modulation Decisions for Wireless Embedded Systems. ISORC 2016: 69-78 - 2015
- [c95]Jonathan C. Beard, Cooper Epstein, Roger D. Chamberlain:
Online Automated Reliability Classification of Queueing Models for Streaming Processing Using Support Vector Machines. Euro-Par 2015: 82-93 - [c94]Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain:
Superoptimizing Memory Subsystems for Multiple Objectives. Euro-Par Workshops 2015: 352-363 - [c93]Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain:
Superoptimized Memory Subsystems for Streaming Applications. FPGA 2015: 126-135 - [c92]Jonathan Curtis Beard, Roger Dean Chamberlain:
Run Time Approximation of Non-blocking Service Rates for Streaming Systems. HPCC/CSS/ICESS 2015: 792-797 - [c91]Michael J. Hall, Roger D. Chamberlain:
Using M/G/l queueing models with vacations to analyze virtualized logic computations. ICCD 2015: 78-85 - [c90]Jonathan C. Beard, Peng Li, Roger D. Chamberlain:
RaftLib: a C++ template library for high performance stream parallel processing. PMAM@PPoPP 2015: 96-105 - [c89]Jonathan C. Beard, Cooper Epstein, Roger D. Chamberlain:
Automated Reliability Classification of Queueing Models for Streaming Computation. ICPE 2015: 325-328 - [i1]Jonathan C. Beard, Roger D. Chamberlain:
Run Time Approximation of Non-blocking Service Rates for Streaming Systems. CoRR abs/1504.00591 (2015) - 2014
- [j20]Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain:
Optimization of Application-Specific Memories. IEEE Comput. Archit. Lett. 13(1): 45-48 (2014) - [j19]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
A memory access model for highly-threaded many-core architectures. Future Gener. Comput. Syst. 30: 202-215 (2014) - [c88]Michael J. Hall, Roger D. Chamberlain:
Performance modeling of virtualized custom logic computations. ASAP 2014: 72-73 - [c87]Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
Performance modeling for highly-threaded many-core GPUs. ASAP 2014: 84-91 - [c86]Jonathan C. Beard, Roger D. Chamberlain:
Use of a Levy Distribution for Modeling Best Case Execution Time Variation. EPEW 2014: 74-88 - [c85]Michael J. Hall, Roger D. Chamberlain:
Performance modeling of virtualized custom logic computations. ACM Great Lakes Symposium on VLSI 2014: 89-90 - [c84]Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
Analysis of classic algorithms on GPUs. HPCS 2014: 65-73 - [c83]Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain:
Orchestrating safe streaming computations with precise control. ICPADS 2014: 1017-1022 - [c82]Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain:
Superoptimization of memory subsystems. LCTES 2014: 145-154 - [c81]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
Theoretical analysis of classic algorithms on highly-threaded many-core GPUs. PPoPP 2014: 391-392 - 2013
- [j18]Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain:
Compiling for power with ScalaPipe. J. Syst. Archit. 59(8): 615-625 (2013) - [c80]Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain:
Adding data parallelism to streaming pipelines for throughput optimization. HiPC 2013: 20-29 - [c79]Jonathan C. Beard, Roger D. Chamberlain:
Use of simple analytic performance models for streaming data applications deployed on diverse architectures. ISPASS 2013: 138-139 - [c78]Jonathan C. Beard, Roger D. Chamberlain:
Analysis of a Simple Approach to Modeling Performance for Streaming Data Applications. MASCOTS 2013: 345-349 - [c77]John Meier, Benjamin Karaus, Sreeharsha Sistla, Terry Tidwell, Roger D. Chamberlain, Christopher D. Gill:
Assessing the appropriateness of using markov decision processes for RF spectrum management. MSWiM 2013: 41-48 - [c76]Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain:
Decomposition techniques for optimal design-space exploration of streaming applications. PPoPP 2013: 285-286 - 2012
- [c75]Lin Ma, Roger D. Chamberlain:
A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines. ASAP 2012: 24-31 - [c74]Joseph G. Wingbermuehle, Roger D. Chamberlain, Ron K. Cytron:
ScalaPipe: A Streaming Application Generator. FCCM 2012: 244 - [c73]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
A Memory Access Model for Highly-threaded Many-core Architectures. ICPADS 2012: 339-347 - [c72]Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain:
Convexity in Non-convex Optimizations of Streaming Applications. ICPADS 2012: 668-675 - [c71]Michael J. Hall, Viktor Gruev, Roger D. Chamberlain:
Performance of a resistance-to-voltage read circuit for sensing magnetic tunnel junctions. MWSCAS 2012: 639-642 - [c70]Jeremy D. Buhler, Kunal Agrawal, Peng Li, Roger D. Chamberlain:
Efficient deadlock avoidance for streaming computation with filtering. PPoPP 2012: 235-246 - 2011
- [c69]Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, Roger D. Chamberlain:
TimeTrial: A low-impact performance profiler for streaming data applications. ASAP 2011: 69-76 - [c68]Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain:
Optimal design-space exploration of streaming applications. ASAP 2011: 227-230 - [c67]John Meier, Christopher D. Gill, Roger D. Chamberlain:
Towards More Effective Spectrum Use Based on Memory Allocation Models. COMPSAC 2011: 426-435 - [c66]Joseph M. Lancaster, Joseph G. Wingbermuehle, Jonathan C. Beard, Roger D. Chamberlain:
Crossing Boundaries in TimeTrial: Monitoring Communications across Architecturally Diverse Computing Platforms. EUC 2011: 280-287 - [c65]Joseph M. Lancaster, Joseph G. Wingbermuehle, Roger D. Chamberlain:
Asking for Performance: Exploiting Developer Intuition to Guide Instrumentation with TimeTrial. HPCC 2011: 321-330 - [c64]Lin Ma, Roger D. Chamberlain, Jeremy D. Buhler, Mark A. Franklin:
Bloom Filter Performance on Graphics Engines. ICPP 2011: 522-531 - [c63]Michael J. Hall, Viktor Gruev, Roger D. Chamberlain:
Noise analysis of a current-mode read circuit for sensing magnetic tunnel junction resistance. ISCAS 2011: 1816-1819 - 2010
- [j17]Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, James H. Buckley, Jeremy Buhler, Greg Galloway, Saurabh Gayen, Michael J. Hall, E. F. Berkley Shands, Naveen Singla:
Auto-Pipe: Streaming Applications on Architecturally Diverse Systems. Computer 43(3): 42-49 (2010) - [c62]Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Design of throughput-optimized arrays from recurrence abstractions. ASAP 2010: 133-140 - [c61]Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, Joseph M. Lancaster:
Deadlock-avoidance for streaming applications with split-join structure: Two case studies. ASAP 2010: 333-336 - [c60]Narayan Ganesan, Roger D. Chamberlain, Jeremy Buhler, Michela Taufer:
Accelerating HMMER on GPUs by implementing hybrid data and task parallelism. BCB 2010: 418-421 - [c59]Roger D. Chamberlain, Joseph M. Lancaster:
Better Languages for More Effective Designing. ERSA 2010: 11-20 - [c58]Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence. FCCM 2010: 87-94 - [c57]Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). FPGA 2010: 286 - [c56]Todd Sproull, Roger D. Chamberlain:
Distributed Algorithms for the Placement of Network Services. International Conference on Internet Computing 2010: 146-152 - [c55]Roger D. Chamberlain, Jeremy Buhler, Mark A. Franklin, James H. Buckley:
Application-guided tool development for architecturally diverse computation. SAC 2010: 496-501 - [c54]Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain:
Deadlock avoidance for streaming computations with filtering. SPAA 2010: 243-252
2000 – 2009
- 2009
- [j16]Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain:
Acceleration of ungapped extension in Mercury BLAST. Microprocess. Microsystems 33(4): 281-289 (2009) - [c53]Octav Chipara, Christopher Brooks, Sangeeta Bhattacharya, Chenyang Lu, Roger D. Chamberlain, Gruia-Catalin Roman, Thomas C. Bailey:
Reliable Real-time Clinical Monitoring Using Sensor Network Technology. AMIA 2009 - [c52]Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
Optimal runtime reconfiguration strategies for systolic arrays. FPL 2009: 162-167 - [c51]Octav Chipara, Christopher Brooks, Sangeeta Bhattacharya, Chenyang Lu, Roger D. Chamberlain, Gruia-Catalin Roman, Thomas C. Bailey:
Poster abstract: Reliable data collection from mobile users for real-time clinical monitoring. IPSN 2009: 397-398 - [c50]Roger D. Chamberlain, Narayan Ganesan:
Sorting on architecturally diverse computer systems. HPRCTA@SC 2009: 39-46 - [c49]Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain:
Efficient runtime performance monitoring of FPGA-based applications. SoCC 2009: 23-28 - 2008
- [j15]Roger D. Chamberlain, Joseph M. Lancaster, Ron K. Cytron:
Visions for application development on hybrid computing systems. Parallel Comput. 34(4-5): 201-216 (2008) - [j14]Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Brandon Harris, Roger D. Chamberlain:
Mercury BLASTP: Accelerating Protein Sequence Alignment. ACM Trans. Reconfigurable Technol. Syst. 1(2): 9:1-9:44 (2008) - [c48]Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain:
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. ASAP 2008: 191-196 - [c47]Praveen Krishnamurthy, Roger D. Chamberlain:
Analytic performance models for bounded queueing systems. IPDPS 2008: 1-8 - [c46]Joseph M. Lancaster, Ron Cytron, Roger D. Chamberlain:
Understanding the performance of streaming applications deployed on hybrid systems. IPDPS 2008: 1-5 - 2007
- [j13]Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Arpith C. Jacob, Joseph M. Lancaster:
Biosequence Similarity Search on the Mercury System. J. VLSI Signal Process. 49(1): 101-121 (2007) - [c45]Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John W. Lockwood, Jason E. Fritts:
Empirical performance assessment using soft-core processors on reconfigurable hardware. Experimental Computer Science 2007: 18 - [c44]Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain:
FPGA-accelerated seed generation in Mercury BLASTP. FCCM 2007: 95-106 - [c43]Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain:
A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. FPL 2007: 765-769 - [c42]Arpith C. Jacob, Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain:
Preliminary results in accelerating profile HMM search on FPGAs. IPDPS 2007: 1-8 - [c41]Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain:
A Federated Simulation Environment for Hybrid Systems. PADS 2007: 198-210 - [c40]Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, Jeremy Buhler, Saurabh Gayen, Patrick Crowley, James H. Buckley:
Application development on hybrid systems. SC 2007: 50 - 2006
- [j12]Scott J. Friedman, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts:
Dusty caches for reference counting garbage collection. SIGARCH Comput. Archit. News 34(1): 3-10 (2006) - [c39]Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho:
Scalable Softcore Vector Processor for Biosequence Applications. FCCM 2006: 295-296 - [c38]Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris:
Accelerator design for protein sequence HMM search. ICS 2006: 288-296 - [c37]Roger D. Chamberlain, Ron K. Cytron, Jason E. Fritts, John W. Lockwood:
Vision for liquid architecture. IPDPS 2006 - [c36]Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood:
Automatic application-specific microarchitecture reconfiguration. IPDPS 2006 - [c35]Gary Stiehr, Roger D. Chamberlain:
Improving cluster utilization through intelligent processor sharing. IPDPS 2006 - 2005
- [j11]Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood:
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. Int. J. Parallel Program. 33(2-3): 115-136 (2005) - [j10]Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan:
VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. J. VLSI Signal Process. 40(1): 57-72 (2005) - [c34]Daniel R. Fuhrmann, Lisandro A. Boggio, John Maschmeyer, Roger D. Chamberlain:
Clutter scattering function estimation and ground moving target detection from multiple STAP datacubes. ICASSP (5) 2005: 593-596 - [c33]Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones:
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. MSE 2005: 97-98 - 2004
- [c32]Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster:
Biosequence Similarity Search on the Mercury System. ASAP 2004: 365-375 - [c31]Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, E. F. Berkley Shands, Jason White:
An Architecture for Fast Processing of Large Unstructured Data Sets. ICCD 2004: 280-287 - [c30]Qiong Zhang, Roger D. Chamberlain, Ronald S. Indeck, Benjamin M. West, Jason White:
Massively Parallel Data Mining Using Reconfigurable Hardware: Approximate String Matching. IPDPS 2004 - 2003
- [c29]Praveen Krishnamurthy, Mark A. Franklin, Roger D. Chamberlain:
Dynamic Reconfiguration of an Optical Interconnect. Annual Simulation Symposium 2003: 89-97 - [c28]Roger D. Chamberlain, Eric Hemmeter, Robert Morley, Jason White:
Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations. Annual Simulation Symposium 2003: 249-255 - [c27]Roger D. Chamberlain, Ron K. Cytron, Mark A. Franklin, Ronald S. Indeck:
The Mercury system: exploiting truly fast hardware for data search. SNAPI@PACT 2003: 65-72 - 2002
- [j9]Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw:
Gemini: An Optical Interconnection Network for Parallel Processing. IEEE Trans. Parallel Distributed Syst. 13(10): 1038-1055 (2002) - [c26]Roger D. Chamberlain, Ch'ng Shi Baw, Mark A. Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton:
Evaluating the Performance of Photonic Interconnection Networks. Annual Simulation Symposium 2002: 209-218 - [c25]Jason E. Fritts, Roger D. Chamberlain:
Breaking the Memory Bottleneck with an Optical Data Path. Annual Simulation Symposium 2002: 352-362 - [c24]Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy:
Optical Network Reconfiguration for Signal Processing Applications. ASAP 2002: 344- - [c23]Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin:
Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. ASAP 2002: 391- - 2001
- [c22]Roger D. Chamberlain, Mark A. Franklin, Abhijit Mahajan:
VLSI Photonic Ring Interconnect for Embedded Multicomputers: Architecture and Performance. PDCS 2001: 351-358 - [c21]Bradley L. Noble, J. Cris Wade, Roger D. Chamberlain:
Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation. Annual Simulation Symposium 2001: 56-64 - 2000
- [c20]Bradley L. Noble, Roger D. Chamberlain:
Analytic performance model for speculative, synchronous, discrete-event simulation. PADS 2000: 30-44
1990 – 1999
- 1999
- [c19]Bradley L. Noble, Roger D. Chamberlain:
Performance Model for Speculative Simulation using Predictive Optimism. HICSS 1999 - [c18]Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin:
Fair Scheduling in an Optical Interconnection Network. MASCOTS 1999: 56-65 - 1996
- [j8]Gregory D. Peterson, Roger D. Chamberlain:
Parallel application performance in a shared resource environment. Distributed Syst. Eng. 3(1): 9-19 (1996) - 1995
- [j7]George Varghese, Roger D. Chamberlain, William E. Weihl:
Deriving Global Virtual Time Algorithms from Conservative Simulation Protocols. Inf. Process. Lett. 54(2): 121-126 (1995) - [j6]Roger D. Chamberlain, Robert R. Krchnavek:
Optically interconnected multicomputers using inverted-graph topologies. IEEE Micro 15(2): 59-69 (1995) - [c17]Roger D. Chamberlain:
Parallel Logic Simulation of VLSI Systems. DAC 1995: 139-143 - [c16]Roger D. Chamberlain, Gregory D. Peterson, Mark A. Franklin, Michael A. Province:
Genetic epidemiology, parallel algorithms, and workstation networks. HICSS (5) 1995: 101-111 - [c15]Bradley L. Noble, Gregory D. Peterson, Roger D. Chamberlain:
Performance of synchronous parallel discrete-event simulation. HICSS (2) 1995: 185-186 - [c14]Gregory D. Peterson, Roger D. Chamberlain:
Stealing cycles: Can we get along? HICSS (2) 1995: 422-441 - [c13]Bradley L. Noble, Roger D. Chamberlain:
Predicting the future: resource requirements and predictive optimism. PADS 1995: 157-164 - 1994
- [j5]Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain:
Parallel Logic Simulation of VLSI Systems. ACM Comput. Surv. 26(3): 255-294 (1994) - [j4]Gregory D. Peterson, Roger D. Chamberlain:
Beyond execution time: expanding the use of performance models. IEEE Parallel Distributed Technol. Syst. Appl. 2(2): 37-49 (1994) - [c12]George Varghese, Roger D. Chamberlain, William E. Weihl:
The pessimism behind optimistic simulation. PADS 1994: 126-131 - [c11]Roger D. Chamberlain, Cheryl D. Henderson:
Evaluating the use of pre-simulation in VLSI circuit partitioning. PADS 1994: 139-146 - [c10]Gregory D. Peterson, Roger D. Chamberlain:
Sharing networked workstations: a performance model. SPDP 1994: 308-315 - 1993
- [c9]Gregory D. Peterson, Roger D. Chamberlain:
Performance of a Globally-Clocked Parallel Simulator. ICPP (3) 1993: 289-298 - [c8]Roger D. Chamberlain, Mark A. Franklin:
Performance Effects of Synchronization in Parallel Processors. SPDP 1993: 611-616 - [c7]Gregory D. Peterson, Roger D. Chamberlain:
Exploiting lookahead in synchronous parallel simulation. WSC 1993: 706-712 - 1991
- [j3]Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin:
Parallel Simulated Annealing using Speculative Computation. IEEE Trans. Parallel Distributed Syst. 2(4): 483-494 (1991) - [c6]Roger D. Chamberlain, Mark A. Franklin:
Analysis of Parallel Mixed-Mode Simulation Algorithms. IPPS 1991: 155-160 - 1990
- [j2]Roger D. Chamberlain, Mark A. Franklin:
Hierarchical discrete-event simulation on hypercube architectures. IEEE Micro 10(4): 10-20 (1990) - [c5]Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin:
Task assignment by parallel simulated annealing. ICCD 1990: 74-77 - [c4]Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin:
Parallel Simulated Annealing Using Speculative Computation. ICPP (3) 1990: 286-290
1980 – 1989
- 1988
- [c3]Roger D. Chamberlain, Mark A. Franklin:
Discrete-event simulation on hypercube architectures. ICCAD 1988: 272-275 - [c2]Roger D. Chamberlain, Mark N. Edelman, Mark A. Franklin, Ellen E. Witte:
Simulated annealing on a multiprocessor. ICCD 1988: 540-544 - 1986
- [j1]Roger D. Chamberlain, Mark A. Franklin:
Collecting Data About Logic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3): 405-412 (1986) - [c1]Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, Brian L. Shing:
Statistics on logic simulation. DAC 1986: 13-19
Coauthor Index
Jonathan C. Beard
aka: Jonathan Curtis Beard
aka: Jonathan Curtis Beard
Jeremy Buhler
aka: Jeremy D. Buhler
aka: Jeremy D. Buhler
Ron Cytron
aka: Ron K. Cytron
aka: Ron K. Cytron
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