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ORCIDITC 1994: Washington, DC, USA
- Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994. IEEE Computer Society 1994, ISBN 0-7803-2103-0
Session 1: Plenary
Invited Address
- Robert E. Anderson:
A Test Retrospection and a Quest for Direction. ITC 1994: 11
Keynote Address
- Aart J. de Geus:
Test: The New Value-Added Field. ITC 1994: 12
Invited Address
- Walt Wilson:
Faster, Better, Cheaper: What Does This Mean For The Test Industry? ITC 1994: 13
Session 2: Known-Good-Die Impact on MCM Testing
- Lina Prokopchak:
Development of a Solution for Achieving Known-Good-Die. 15-21 - Toshiaki Ueno, You Kondoh:
Membrane Prove Technology for MCM Known-Good-Die. 22-29 - William E. Burdick Jr., Wolfgang Daum:
High-Yield Multichip Modules Based on Minimal IC Pretest. 30-40 - Anne E. Gattiker, Wojciech Maly:
Feasibility Study of Smart Substrate Multichip Modules. 41-49
Session 3: Microprocessor Test
- Dilip K. Bhavsar, John H. Edmondson:
Testability Strategy of the ALPHA AXP 21164 Microprocessor. 50-59 - Alfred L. Crouch, Matthew Pressly, Joe Circello:
Testabilty Features of the MC 68060 Microprocessor. 60-69 - Kalon Holdbrook, Sunil Joshi, Samir Mitra, Joe Petolino, Renu Raman, Michelle Wong:
microSPARCTM: A Case Study of Scan-Based Debug. 70-75 - Craig Hunter, E. Kofi Vida-Torku, Johnny J. LeBlanc:
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor. 76-83
Session 4: Test Strategy and the Bottom Line
- Des Farren, Anthony P. Ambler:
System Test Cost Modelling Based on Event Rate Analysis. 84-92 - Donald L. Wheater, Phil Nigh, Jeanne Trinko Mechler, Luke Lacroix:
ASIC Test Cost/Strategy Trade-offs. 93-102 - Timothy J. Moore:
A Test Process Optimization and Cost Modeling Tool. 103-110 - David A. Greene:
When Does It Make cents to Give Up Physical Test Access? 111-119
Session 5: Structured Methodologies for System Test
- Edward C. Behnke:
3B21D BIST/Boundary-Scan System Diagnostic Test Story. 120-126 - Frank W. Angelotti:
Modeling for Structured System Interconnect Test. 127-133 - Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee:
System-Level Testability of Hardware/Software Systems. 134-142 - John D. Lofgren:
A Generic Test and Maintenance Node for Embedded System Test. 143-153
Session 6: Delay Testing and Synthesis
- Bill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk:
Fastpath: A Path-Delay Test Generator for Standard Scan Designs. 154-163 - Prab Varma:
On Path-Delay Testing in a Standard Scan Environment. 164-173 - Nur A. Touba, Edward J. McCluskey:
Automated Logic Synthesis of Random-Pattern-Testable Circuits. 174-183 - Sujit Dey, Miodrag Potkonjak:
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. 184-193
Session 7: Paving the Superhighway to Ultimate CMOS IC Quality
- Keith Baker:
QTAG: A Standard for Test Fixture Based IDDQ/ISSQ Monitors. 194-202 - Hans A. R. Manhaeve, Paul L. Wrighton, Jos van Sas, Urbain Swerts:
An Off-chip IDDQ Current Measurement Unit for Telecommunication ASICs. 203-212 - Keith Baker, A. H. Bratt, Andrew Richardson, A. Welbers:
Development of a CLASS 1 QTAG Monitor. 213-222 - Alan Hales:
A Serially Addressable, Flexible Current Monitor for Test Fixture Based IDDQ/ISSQ Testing. 223-232
Session 8: Sequential Test Generation
- Jalal A. Wehbeh, Daniel G. Saab:
On the Initialization of Sequential Circuits. 233-239 - Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
:
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. 240-249 - Seongmoon Wang, Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Test Application. 250-258 - Mahesh A. Iyer, Miron Abramovici:
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). 259-266
Session 9: ATE Topics
- Michael G. Davis:
Implementation of a Dual-Segment Architecture for a High-Pin-Count VLSI Test System. 267-272 - Didier Wimmers, Kris Sakaitani, Burnell G. West:
500-MHz Testing on a 100-MHz Tester. 273-278 - Mary Sue Haydt, Robert Owens, Samiha Mourad:
Modeling the Effect of Ground Bounce on Noise Margin. 279-285 - Eric Kushnick:
Modular Mixed Signal Testing: High Speed or High Resolution. 286-290
Session 10: System-Level Applications of BIST, Boundary-Scan, DFT
- Gordon R. McLeod:
Built-in System Test and Fault Location. 291-299 - John Andrews:
Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test Programs. 300-306 - Duy Le, Ivan Karolik, Ronald Smith, A. J. Mcgovern, Chyral Curette, Joseph Ulbin, Michael Zarubaiko, Charles Henry, Lewis Stevens:
Environmental Stress Testing with Boundary-Scan. 307-313 - Lee Whetsel:
An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures. 314-322
Session 11: DFT by Clock Manipulation
- Kee Sup Kim, Len Schultz:
Multi-Frequency, Multi-Phase Scan Chain. 323-330 - Jau-Shien Chang, Chen-Shang Lin:
A Test-Clock Reduction Method for Scan-Designed Circuits. 331-339 - Sanghyeon Baeg, William A. Rogers:
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. 340-349 - André DeHon:
In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. 350-359
Session 13 - Panel: Testing High-Speed DRAMs
- Yasuhiro Konishi, Toshiyuki Ogawa, Masaki Kumanoya:
Testing 256k Word x 16 Bit Cache DRAM (CDRAM). 360 - James A. Gasbarro:
Testing High Speed Drams. 361 - Kent Stalnaker:
Practical Test Methods for Verification of the EDRAM. 362 - Wha-Joon Lee:
Testing Issues on High Speed Synchronous DRAMs. 363
Session 14 - Panel: Benchmarking Test Tools: Are They Necessary and Why
- Kamalesh N. Ruparel:
Benchmarking. 364 - Don Sterba:
Potential Solutions for Benchmarking Issues. 365
Session 15 - Panel: MCM Testing: Is It Board Test or IC Test?
- Kenneth E. Posse:
Multichip Module Testing Methodologies: What's In; What's Not. 366 - Jed Eastman:
MCM Test Trade-Offs. 367
Session 17: Applications of Memory BIST
- Vyacheslav N. Yarmolik, Michael Nicolaidis, O. Kebichi:
Aliasing-free Signature Analysis for RAM BIST. 368-377 - Yervant Zorian, Ad J. van de Goor, Ivo Schanstra:
An Effective BIST Scheme for Ring-Address Type FIFOs. 378-387 - Craig Hunter, Jeff Slaton, Jim Eno, Romesh M. Jessani, Carl Dietz:
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism. 388-394
Session 18: Test Strategies for CMOS ICs
- Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee:
Testing CMOS Logic Gates for Realistic Shorts. 395-402 - Sreejit Chakravarty, Paul J. Thadikaran:
A Study of IDDQ Subset Selection Algorithms for Bridging Faults. 403-412 - Charles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson:
Defect Classes - An Overdue Paradigm for CMOS IC. 413-425
Session 19: MCM Test Strategies
- Thomas M. Storey, C. Lapihuska, E. Atwood, L. Su:
A Test Methodology to Support an ASEM MCM Foundry. 426-435 - Andrew Flint:
Test Strategies for a Family of Complex MCMs. 436-445 - Najmi T. Jarwala:
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules. 446-455
Session 20: Test Engineering Accuracy
- Jerry Katz:
A Case Study in the Use of Scan in microSparcTM Testing and Debug. 456-460 - Thomas Burch, Joachim Hartmann, Günter Hotz, M. Krallmann, U. Nikolaus, Sudhakar M. Reddy, Uwe Sparmann:
A Hierarchical Environment for Interactive Test Engineering. 461-470 - Solomon Max:
Ensuring System Traceability to International Standards. 471-480
Session 21: Hardware Pattern Generation and Compression
- Dhiraj K. Pradhan, Mitrajit Chatterjee:
GLFSR - A New Test Pattern Generator for Built-In Self-Test. 481-490 - Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
Design of an Efficient Weighted-Random-Pattern Generation System. 491-500 - Krishnendu Chakrabarty, John P. Hayes:
Efficient Test-Response Compression for Multiple-Output Cicuits. 501-510
Session 22: Practical Memory Testing
- Timothy J. Dell:
ECC-On-SIMM Test Challenges. 511-515 - James A. Gasbarro, Mark Horowitz:
Techniques for Characterizing DRAMs With a 500-MHz Interface. 516-525 - Sangchul Oh, Jae-Ho Kim, Ho-Jeong Choi, Si-Don Choi, Ki Tae Park, Jong-Woo Park, Wha-Joon Lee:
Automatic Failure-Analysis System for High-Density DRAM. 526-530
Session 23: The Test Engineer's Role in...
... IC Test
- William R. Kosar:
Detection and Correction of Systematic Type 1 Test Errors Through Concurrent Engineering. 531-538
... Board Test
- Mick Tegethoff, Tom Chen:
Defects, Fault Coverage, Yield and Cost in Board Manufacturing. 539-547
... System Test
- Cheryl Ascarrunz:
HALT: Bridging the Gap Between Theory and Practice. 548-554
Session 24: Defect, Quality, and Cost Concerns for CMOS ICs
- Simon Johnson:
Residual Charge on the Faulty Floating Gate MOS Transistor. 555-561 - Eric Bruls:
Variable Supply Voltage Testing for Analogue CMOS and Bipolar Circuits. 562-571 - Scott Davidson:
Is IDDQ Yield Loss Inevitable? 572-579
Session 25: Software Environments for ATE
- John A. Masciola, Gerald K. Morgan, Geoffrey L. Templeton:
A Software Architecture for Mixed-Signal Functional Testing. 580-586 - Gregory A. Maston:
A Procedural Interface to Test. 587-593 - Yuning Sun, Xiaoming Wang, Wanchun Shi:
An Intelligent Software-Integrated Environment of IC Testing. 594-603
Session 26: Real Fault Simulation for Real Circuits
- J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. 604-613 - Rolf Krieger, Bernd Becker, Martin Keim:
A Hybrid Fault Simulator for Synchronous Sequential Circuits. 614-623 - Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Reduced Scan Shift: A New Testing Method for Sequential Circuit. 624-630
Session 27: Design for Test Considerations for Mixed-Signal Devices
- Mustapha Slamani, Bozena Kaminska, Guy Quesnel:
An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected Parameters. 631-640 - R. J. A. Harvey, Andrew Mark David Richardson, Eric Bruls, Keith Baker:
Analogue Fault Simulation Based on Layout-Dependent Fault Models. 641-649 - A. K. Lu, Gordon W. Roberts:
An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications. 650-659
Session 28: Boundary Scan Design Techniques
- Alfred L. Crouch, Rick Ramus, Colin M. Maunder:
Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution. 660-669 - Chauchin Su, Kychin Hwang, Shyh-Jye Jou:
An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. 670-676 - Savio N. Chau:
Fault Injection Boundary-Scan Design for Verification of Fault-Tolerant Systems. 677-682
Session 29: ATE PIN Electronics, Timing, and Accuracy
- Takashi Sekino, Toshiyuki Okayasu:
Ultra Hi-Speed Pin-Electronics and Test Station Using GaAs IC. 683-690 - Dennis Petrich:
Achieving +/-30ps Accuracy in the ATE Environment. 691-700 - Marc Mydill:
A Test-System Architecture to Reduce Transmission Line Effects During High-Speed Testing. 701-709 - Ewa Sokolowska, Bozena Kaminska:
Application of Optoelectronic Techniques to High Speed Testing. 710-719
Session 30: Towards Quantifying Defect Coverage
- Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. 720-728 - Olaf Stern, Hans-Joachim Wunderlich:
Simulation Results of an Efficient Defect-Analysis Procedure. 729-738 - Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman:
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. 739-746
Session 31: New Test Technique Developments for Mixed Signal Devices
- Frank Bouwman, Taco Zwemstra, Sonny Hartanto, Keith Baker, Jan Koopmans:
Application of Joint Time-Frequency Analysis in Mixed-Signal Testing. 747-756 - Luke S. L. Hsieh, Sandeep P. Kumar:
Digitizer Error Extraction in the Nonlinearity Test. 757-762 - Yves Langard, Jean-Luc Balat, Jacques Durand:
An Improved Method of ADC Jitter Measurement. 763-770
Session 32: Test Data Systems, Teams, and Results
- Gregory W. Papadeas, David Gauthier:
An On-Line Data Collection and Analysis System for VLSI Devices at Wafer Probe and Final Test. 771-780 - Scott A. Erjavic:
Test Station Workcell Controller and Resource Relationship Design. 781-792 - Tamorah Comard, Madhukar Joshi, Donald A. Morin, Kimberley Sprague:
Calculating Error of Measurement on High-Speed Microprocessor Test. 793-801
Session 33: Effective Board-Level Test Vector Generation
- Douglas W. Raymond, Philip J. Stringer, Harold W. Ng, Michael Mitsumata, Robert Burk:
Goal-Directed Vector Generation Using Sample ICs. 802-810 - Gordon D. Robinson:
NAND Trees Accurately Diagnose Board-Level Pin Faults. 811-816 - Douglas W. Raymond, Dominic F. Haigh, Ray Bodick, Barbara Ryan, Dale McCombs:
Non-Volatile Programmable Devices and In-Circuit Test. 817-823
Session 34: Software Testing Tools
- A. Jefferson Offutt:
A Practical System for Mutation Testing: Help for the Common Programmer. 824-830 - Hwei Yin, James M. Bieman:
Improving Software Testability with Assertion Insertion. 831-839 - Anneliese von Mayrhauser, Jeff Walls, Richard T. Mraz:
Sleuth: A Domain-Based Testing Tool. 840-849
Session 35: Memory Test Algorithms
- Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb:
Efficient O(sqrt(n)) BIST Algorithms for DDNPS Faults in Dual-Port Memories. 850-859 - Mark G. Karpovsky, Vyacheslav N. Yarmolik:
Transparent Memory Testing for Pattern-Sensitive Faults. 860-869 - Ad J. van de Goor, B. Smit:
Generating March Tests Automatically. 870-878
Session 36: DFT in Practice
- Ralph Sanchez:
Concurrent Engineering with DFT in the Digital System: A Parallel Process. 879-886 - Cecil A. Dean, Yervant Zorian:
Do You Practice Safe Tests? What We Found Out About Your Habits. 887-892 - Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer:
Control Strategies for Chip-Based DFT/BIST Hardware. 893-902
Session 37: Board Test Opportunities and Solutions
- Mick Tegethoff, Tom Chen:
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. 903-910 - Lars Eerenstein:
Testing Two Generations of HDTV Decoders - The Impact of Boundary-Scan. 911-918 - Yunsheng Lu, Weiwei Mao, Ramaswami Dandapani, Ravi K. Gulati:
Structure and Metrology for a Single-wire Analog. 919-928
Session 38: Innovation in Logic BIST
- Mohammed F. AlShaibi, Charles R. Kime:
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits. 929-938 - Albrecht P. Stroele, Hans-Joachim Wunderlich:
Configuring Flip-Flops to BIST Registers. 939-948 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Making the Circular Self-Test Path Technique Effective for Real Circuits. 949-957
Session 39: High-Level Test Generation
- R. S. Ramchandani, Donald E. Thomas:
Behavioral-Test Generation using Mixed-Integer Non-linear Programming. 958-967 - Chang Hyun Cho, James R. Armstrong:
B-algorithm: A Behavioral-Test Generation Algorithm. 968-979 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Full-Symbolic ATPG for Large Circuits. 980-988
Session 40: Test-Synthesis Practices
- Henry Cox:
On Synthesizing Circuits With Implicit Testability Constraints. 989-998 - Edward B. Pitty, Denis Martin, Hi-Kyeung Tony Ma:
A Simulation-Based Protocol-Driven Scan-Test-Design Rule Checker. 999-1006 - Irith Pomeranz, Sudhakar M. Reddy:
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. 1007-1016
Session 41 - Panel: Testers and Testing in the Next Ten Years
- Wojciech Maly:
Integration of Design, Manufacturing and Testing. 1017
Session 43 - Panel: Which Backplane Test Interfaces Should I Use?
- Lee Whetsel:
Navigating Test Access in Systems. 1018 - John Andrews:
Using SCANTM Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test Bus. 1019 - Patrick F. McHugh:
The IEEE P1149.5 MTM-Bus, A Backplane Test and Initialization Interface. 1020 - Cary Champlin:
Backplane Test Bus Selection Criteria. 1021 - Robert Gage:
1149.1 Scan Control Transport Levels. 1022
Session 44 - Panel: Boundary Scan: It Is Time To Go beyond Its Boundaries
- Kenneth P. Parker:
Observations on the 1149.x Family of Standards. 1023 - William Eklow:
Optimizing Boundary Scan in a Proprietary Environment. 1024
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