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ORCIDChip-Hong Chang
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- affiliation (PhD 1998): Nanyang Technological University, Singapore
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2020 – today
- 2024
[j109]Yi Wang
, Jing Xiao, Zhengzhe Wei, Yuanjin Zheng, Kea-Tiong Tang, Chip-Hong Chang:
Security and Functional Safety for AI in Embedded Automotive System - A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1701-1707 (2024)- [j108]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. 19: 6604-6619 (2024) - [c161]Ying Tao, Chip-Hong Chang, Sylvain Saïghi, Shengyu Gao:
GaitSpike: Event-based Gait Recognition With Spiking Neural Network. AICAS 2024: 357-361 - [c160]Pierre Lewden, Adrien F. Vincent, Jean Tomas, Chip-Hong Chang, Sylvain Saïghi:
Effect of Line Resistance of Passive Memristive Crossbars on Spiking Neural Network Performance. AICAS 2024: 403-407 - [c159]Qi Cui, Ruohan Meng, Chaohui Xu, Chip-Hong Chang:
Steganographic Passport: An Owner and User Verifiable Credential for Deep Model IP Protection Without Retraining. CVPR 2024: 12302-12311 - [c158]Wenye Liu, Nazim Altar Koca, Chip-Hong Chang:
Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning Aggregation. DATE 2024: 1-6 - [c157]Bowen Hu, Weiyang He, Si Wang, Wenye Liu, Chip-Hong Chang:
Live Demonstration: Man-in-the-Middle Attack on Edge Artificial Intelligence. ISCAS 2024: 1 - [c156]Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar:
Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. ISCAS 2024: 1-5 - [c155]Haibiao Zuo, Xiaoliang Huang, Shiqiao Zhang, Chip-Hong Chang, Xiaojin Zhao:
An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for Trustworthy Sensing. VLSI Technology and Circuits 2024: 1-2 - [i8]Qi Cui, Ruohan Meng, Chaohui Xu, Chip-Hong Chang:
Steganographic Passport: An Owner and User Verifiable Credential for Deep Model IP Protection Without Retraining. CoRR abs/2404.02889 (2024) - [i7]Chaohui Xu, Si Wang, Chip-Hong Chang:
BadHMP: Backdoor Attack against Human Motion Prediction. CoRR abs/2409.19638 (2024) - [i6]Chaohui Xu, Qi Cui, Jinxin Dong, Weiyang He, Chip-Hong Chang:
IDEA: An Inverse Domain Expert Adaptation Based Active DNN IP Protection Method. CoRR abs/2410.00059 (2024) - 2023
- [j107]Chip-Hong Chang, Stefan Katzenbeisser, Debdeep Mukhopadhyay, Ulrich Rührmair:
The ASHES 2021 special issue at JCEN. J. Cryptogr. Eng. 13(4): 389-390 (2023) - [j106]Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li:
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1504-1517 (2023) - [j105]Yuan Cao, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye, Lei Qian, Chip-Hong Chang:
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4900-4913 (2023) - [j104]Chip-Hong Chang, Pingqiang Zhou, Yuan Cao, Qiang Liu:
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022). IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5009-5010 (2023) - [j103]Chaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang:
An Imperceptible Data Augmentation Based Blackbox Clean-Label Backdoor Attack on Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5011-5024 (2023) - [j102]Yue Zheng, Wenye Liu, Chongyan Gu, Chip-Hong Chang:
PUF-Based Mutual Authentication and Key Exchange Protocol for Peer-to-Peer IoT Applications. IEEE Trans. Dependable Secur. Comput. 20(4): 3299-3316 (2023) - [c154]Chaoqun Liu, Wenxuan Zhang, Guizhen Chen, Xiaobao Wu, Anh Tuan Luu, Chip-Hong Chang, Lidong Bing:
Zero-Shot Text Classification via Self-Supervised Tuning. ACL (Findings) 2023: 1743-1761 - [c153]Weiyang He, Zizhen Liu, Chip-Hong Chang:
An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks. ATS 2023: 1-6 - [c152]Lejla Batina, Chip-Hong Chang, Domenic Forte, Ulrich Rührmair:
ASHES '23: Workshop on Attacks and Solutions in Hardware Security. CCS 2023: 3664-3665 - [c151]Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li:
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE 2023: 1-2 - [c150]Xiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang:
MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator. ICFPT 2023: 188-197 - [c149]Jie Ma, Junqing Zhang, Guanxiong Shen, Alan Marshall, Chip-Hong Chang:
White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification. ICC 2023: 3714-3719 - [c148]Nazim Altar Koca, Anh Tuan Do, Chip-Hong Chang:
Hardware-efficient Softmax Approximation for Self-Attention Networks. ISCAS 2023: 1-5 - [c147]Yue Zheng, Wenye Liu, Chip-Hong Chang:
A Lightweight PUF-based Secure Group Key Agreement Protocol for Wireless Sensor Networks. ISCAS 2023: 1-5 - [e9]Chip-Hong Chang, Ulrich Rührmair, Lejla Batina, Domenic Forte:
Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security, ASHES 2023, Copenhagen, Denmark, 30 November 2023. ACM 2023 [contents] - [i5]Chaoqun Liu, Wenxuan Zhang, Guizhen Chen, Xiaobao Wu, Anh Tuan Luu, Chip-Hong Chang, Lidong Bing:
Zero-Shot Text Classification via Self-Supervised Tuning. CoRR abs/2305.11442 (2023) - [i4]Xiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang:
Mercury: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator. CoRR abs/2308.01193 (2023) - [i3]Jie Ma, Junqing Zhang, Guanxiong Shen, Alan Marshall, Chip-Hong Chang:
White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification. CoRR abs/2308.07433 (2023) - [i2]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR abs/2309.10607 (2023) - [i1]Xiaobei Yan, Chip-Hong Chang, Tianwei Zhang:
Defense against ML-based Power Side-channel Attacks on DNN Accelerators with Adversarial Attacks. CoRR abs/2312.04035 (2023) - 2022
- [j101]Chip-Hong Chang, Stefan Katzenbeisser, Ulrich Rührmair, Patrick Schaumont:
The ASHES 2020 special issue at JCEN. J. Cryptogr. Eng. 12(4): 369-370 (2022) - [j100]Junqing Zhang, Chip-Hong Chang, Chongyan Gu, Lajos Hanzo:
Radio Frequency Fingerprints vs. Physical Unclonable Functions - Are They Twins, Competitors, or Allies? IEEE Netw. 36(6): 68-75 (2022) - [j99]Yuan Cao, Xiaojin Zhao, Wenhan Zheng, Yue Zheng, Chip-Hong Chang:
A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 272-283 (2022) - [j98]Yuan Cao, Yanze Wu, Wen Wang, Xu Lu, Shuai Chen, Jing Ye, Chip-Hong Chang:
An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 682-693 (2022) - [j97]Yuan Cao, Yanze Wu, Lan Qin, Shuai Chen, Chip-Hong Chang:
Area, Time and Energy Efficient Multicore Hardware Accelerators for Extended Merkle Signature Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4908-4918 (2022) - [j96]Yue Zheng, Si Wang, Chip-Hong Chang:
A DNN Fingerprint for Non-Repudiable Model Ownership Identification and Piracy Detection. IEEE Trans. Inf. Forensics Secur. 17: 2977-2989 (2022) - [c146]Si Wang, Chaohui Xu, Yue Zheng, Chip-Hong Chang:
A Buyer-traceable DNN Model IP Protection Method Against Piracy and Misappropriation. AICAS 2022: 308-311 - [c145]Yuxin Lin, Wenye Liu, Chip-Hong Chang:
Deep Texture-Depth-Based Attention for Face Recognition on IoT Devices. APCCAS 2022: 1-5 - [c144]Chip-Hong Chang, Domenic Forte, Debdeep Mukhopadhyay, Ulrich Rührmair:
ASHES 2022 - 6th Workshop on Attacks and Solutions in Hardware Security. CCS 2022: 3545-3547 - [c143]Wenye Liu, Weiyang He, Bowen Hu, Chip-Hong Chang:
A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane. SOCC 2022: 1-6 - [c142]Chaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang:
Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks. SOCC 2022: 1-6 - [e8]Chip-Hong Chang, Ulrich Rührmair, Debdeep Mukhopadhyay, Domenic Forte:
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, ASHES 2022, Los Angeles, CA, USA, 11 November 2022. ACM 2022, ISBN 978-1-4503-9884-8 [contents] - [e7]Victor Grimblatt, Chip-Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera:
VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 661, Springer 2022, ISBN 978-3-031-16817-8 [contents] - 2021
- [j95]Naghmeh Karimi, Kanad Basu, Chip-Hong Chang, Jason M. Fung:
Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 223-227 (2021) - [j94]Wenye Liu, Chip-Hong Chang, Xueyang Wang, Chen Liu, Jason M. Fung, Mohammad Ebrahimabadi, Naghmeh Karimi, Xingyu Meng, Kanad Basu:
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 228-251 (2021) - [j93]Si Wang, Wenye Liu, Chip-Hong Chang:
A New Lightweight In Situ Adversarial Sample Detector for Edge Deep Neural Network. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 252-266 (2021) - [j92]Chip-Hong Chang, Daniel E. Holcomb, Ulrich Rührmair, Patrick Schaumont:
The ASHES 2019 special issue at JCEN. J. Cryptogr. Eng. 11(3): 199-200 (2021) - [j91]Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill:
A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs. J. Cryptogr. Eng. 11(3): 227-238 (2021) - [j90]Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li:
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1010-1038 (2021) - [j89]Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Shichao Yu, Yale Wang, Máire O'Neill:
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1183-1196 (2021) - [j88]Aijiao Cui, Chip-Hong Chang, Wei Zhou, Yue Zheng:
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips. IEEE Trans. Emerg. Top. Comput. 9(2): 1095-1105 (2021) - [j87]Wenye Liu, Chip-Hong Chang, Fan Zhang:
Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint. IEEE Trans. Inf. Forensics Secur. 16: 1928-1942 (2021) - [j86]Aijiao Cui, Chengkang He, Chip-Hong Chang, Hao Lu:
Identification of FSM State Registers by Analytics of Scan-Dump Data. IEEE Trans. Inf. Forensics Secur. 16: 5138-5153 (2021) - [c141]Lijuan Han, Yuan Cao, Lei Qian, Haodong Xie, Chip-Hong Chang:
An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator. AsianHOST 2021: 1-6 - [c140]Wenye Liu, Chip-Hong Chang:
A Forward Error Compensation Approach for Fault Resilient Deep Neural Network Accelerator Design. ASHES@CCS 2021: 41-50 - [c139]Jian Xian Soo, Yue Zheng, Chip-Hong Chang:
Live Demonstration: Event-Driven Physical Unclonable Function for Proactive Monitoring System by Dynamic Vision Sensor. ISCAS 2021: 1 - [c138]Si Wang, Chip-Hong Chang:
Fingerprinting Deep Neural Networks - a DeepFool Approach. ISCAS 2021: 1-5 - [c137]Yue Zheng, Chip-Hong Chang:
Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints. ISCAS 2021: 1-5 - [e6]Chip-Hong Chang, Ulrich Rührmair, Stefan Katzenbeisser, Debdeep Mukhopadhyay:
ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, Virtual Event, Republic of Korea, 19 November 2021. ACM 2021, ISBN 978-1-4503-8662-3 [contents] - 2020
- [j85]Yue Zheng, Yuan Cao, Chip-Hong Chang:
A PUF-Based Data-Device Hash for Tampered Image Detection and Source Camera Identification. IEEE Trans. Inf. Forensics Secur. 15: 620-634 (2020) - [j84]Yue Zheng, Xiaojin Zhao, Takashi Sato, Yuan Cao, Chip-Hong Chang:
Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System. IEEE Trans. Inf. Forensics Secur. 15: 2824-2839 (2020) - [j83]ShuMin Liu, Jiajia Chen, Yuan Xun, Xiaojin Zhao, Chip-Hong Chang:
A New Polarization Image Demosaicking Algorithm by Exploiting Inter-Channel Correlations With Guided Filtering. IEEE Trans. Image Process. 29: 7076-7089 (2020) - [j82]Qiang Zhao, Yiheng Wu, Xiaojin Zhao, Yuan Cao, Chip-Hong Chang:
A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1449-1460 (2020) - [c136]Chip-Hong Chang, Stefan Katzenbeisser, Ulrich Rührmair, Patrick Schaumont:
ASHES 2020: 4th Workshop on Attacks and Solutions in Hardware Security. CCS 2020: 2145-2146 - [c135]Wenye Liu, Chip-Hong Chang, Fan Zhang, Xiaoxuan Lou:
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection. DAC 2020: 1-6 - [c134]Nimesh Shah, Sumon Kumar Bose, Chip-Hong Chang, Arindam Basu:
Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling. ISCAS 2020: 1-5 - [c133]Si Wang, Wenye Liu, Chip-Hong Chang:
Fired Neuron Rate Based Decision Tree for Detection of Adversarial Examples in DNNs. ISCAS 2020: 1-5 - [e5]Chip-Hong Chang, Ulrich Rührmair, Stefan Katzenbeisser, Patrick Schaumont:
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2020, Virtual Event, USA, November 13, 2020. ACM 2020, ISBN 978-1-4503-8090-4 [contents]
2010 – 2019
- 2019
- [j81]Gelei Deng, Jiajia Chen, Jiaxuan Zhang, Chip-Hong Chang:
Area- and Power-Efficient Nearly-Linear Phase Response IIR Filter by Iterative Convex Optimization. IEEE Access 7: 22952-22965 (2019) - [j80]Yuan Cao, Wenhan Zheng, Xiaojin Zhao, Chip-Hong Chang:
An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability. IEEE Access 7: 105287-105297 (2019) - [j79]Chip-Hong Chang, Marten van Dijk, Ulrich Rührmair, Mark M. Tehranipoor:
Emerging Attacks and Solutions for Secure Hardware in the Internet of Things. IEEE Trans. Dependable Secur. Comput. 16(3): 373-375 (2019) - [j78]Yue Zheng, Yuan Cao, Chip-Hong Chang:
UDhashing: Physical Unclonable Function-Based User-Device Hash for Endpoint Authentication. IEEE Trans. Ind. Electron. 66(12): 9559-9570 (2019) - [j77]Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang:
Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response. IEEE Trans. Inf. Forensics Secur. 14(4): 1109-1123 (2019) - [j76]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c132]Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Shichao Yu, Qingqing Ma, Máire O'Neill:
A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication. AsianHOST 2019: 1-6 - [c131]Chengkang He, Aijiao Cui, Chip-Hong Chang:
Identification of State Registers of FSM Through Full Scan by Data Analytics. AsianHOST 2019: 1-6 - [c130]Wenye Liu, Si Wang, Chip-Hong Chang:
Vulnerability Analysis on Noise-Injection Based Hardware Attack on Deep Neural Networks. AsianHOST 2019: 1-6 - [c129]Si Wang, Wenye Liu, Chip-Hong Chang:
Detecting Adversarial Examples for Deep Neural Networks via Layer Directed Discriminative Noise Injection. AsianHOST 2019: 1-6 - [c128]Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill:
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs. ASHES@CCS 2019: 101-106 - [c127]Chip-Hong Chang, Daniel E. Holcomb, Francesco Regazzoni, Ulrich Rührmair, Patrick Schaumont:
ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security. CCS 2019: 2709-2710 - [c126]Wenye Liu, Chip-Hong Chang:
Analysis of Circuit Aging on Accuracy Degradation of Deep Neural Network Accelerator. ISCAS 2019: 1-5 - [c125]Kai Wang, Yuan Cao, Chip-Hong Chang, Xiaoli Ji:
High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability. ISCAS 2019: 1-5 - [c124]Biyin Wang, Xiaojin Zhao, Yue Zheng, Chip-Hong Chang:
An In-Pixel Gain Amplifier Based Event-Driven Physical Unclonable Function for CMOS Dynamic Vision Sensors. ISCAS 2019: 1-5 - [c123]Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang:
A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. ISCAS 2019: 1-5 - [e4]Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Patrick Schaumont:
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15, 2019. ACM 2019, ISBN 978-1-4503-6839-1 [contents] - 2018
- [j75]Jiajia Chen, Chip-Hong Chang, Yujia Wang, Juan Zhao, Susanto Rahardja:
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 896-900 (2018) - [j74]Jiajia Chen, Chip-Hong Chang, Jiatao Ding, Rui Qiao, Mathias Faust:
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 712-722 (2018) - [j73]Zheng Wang, Yi Chen, Aakash Patil, Jayasanker Jayabalan, Xueyong Zhang, Chip-Hong Chang, Arindam Basu:
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1314-1326 (2018) - [j72]Yuan Cao, Chao Qun Liu, Chip-Hong Chang:
A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3864-3873 (2018) - [j71]ShuMin Liu, Jiajia Chen, Chip-Hong Chang, Ye Ai:
A New Accurate and Fast Homography Computation Algorithm for Sports and Traffic Video Analysis. IEEE Trans. Circuits Syst. Video Technol. 28(10): 2993-3006 (2018) - [c122]Chip-Hong Chang, Jorge Guajardo, Daniel E. Holcomb, Francesco Regazzoni, Ulrich Rührmair:
ASHES 2018- Workshop on Attacks and Solutions in Hardware Security. CCS 2018: 2168-2170 - [c121]Yuan Cao, Yunyi Guo, Benyu Liu, Wei Ge, Min Zhu, Chip-Hong Chang:
A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing. ICCCN 2018: 1-8 - [c120]Yue Zheng, Yuan Cao, Chip-Hong Chang:
Facial biohashing based user-device physical unclonable function for bring your own device security. ICCE 2018: 1-6 - [c119]Truong Phu Truan Ho, Chip-Hong Chang:
Towards Ideal Lattice-Based Cryptography on ASIC: A Custom Implementation of Number Theoretic Transform. DSP 2018: 1-5 - [c118]Qiang Zhao, Yuan Cao, Xiaojin Zhao, Chip-Hong Chang:
A Current Comparator Based Physical Unclonable Function with High Reliability and Energy Efficiency. DSP 2018: 1-4 - [c117]Yuan Cao, Chip-Hong Chang, Wenhan Zheng, Xiaojin Zhao:
A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References. ISCAS 2018: 1-5 - [c116]Sumedh Somnath Dhabu, Yue Zheng, Wenye Liu, Chip-Hong Chang:
Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test. ISCAS 2018: 1-5 - [c115]Yue Zheng, Sumedh Somnath Dhabu, Chip-Hong Chang:
Securing IoT Monitoring Device using PUF and Physical Layer Authentication. ISCAS 2018: 1-5 - [e3]Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Jorge Guajardo:
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2018, Toronto, ON, Canada, October 19, 2018. ACM 2018, ISBN 978-1-4503-5996-2 [contents] - 2017
- [j70]Sachin Kumar, Chip-Hong Chang, Thian Fatt Tay:
New Algorithm for Signed Integer Comparison in {2n+k, 2n-1, 2n+1, 2n±1-1} and Its Efficient Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1481-1493 (2017) - [j69]Jiajia Chen, Jinghong Tan, Chip-Hong Chang, Feng Feng:
A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1588-1598 (2017) - [j68]Chao Qun Liu, Yuan Cao, Chip-Hong Chang:
ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3138-3149 (2017) - [j67]Aijiao Cui, Yanhui Luo, Chip-Hong Chang:
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks. IEEE Trans. Inf. Forensics Secur. 12(2): 363-376 (2017) - [j66]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j65]Sachin Kumar, Chip-Hong Chang:
A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2n-1, 2n, 2n+ 1, 2n+1-1, 2n-1-1. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3521-3533 (2017) - [c114]Yuan Cao, Chip-Hong Chang, Yue Zheng, Xiaojin Zhao:
An energy-efficient true random number generator based on current starved ring oscillators. AsianHOST 2017: 37-42 - [c113]Chip-Hong Chang, Marten van Dijk, Farinaz Koushanfar, Ulrich Rührmair, Mark M. Tehranipoor:
ASHES 2017: Workshop on Attacks and Solutions in Hardware Security. CCS 2017: 2623-2625 - [c112]Xiaonan Huang, Aijiao Cui, Chip-Hong Chang:
A new watermarking scheme on scan chain ordering for hard IP protection. ISCAS 2017: 1-4 - [c111]Chao Qun Liu, Yue Zheng, Chip-Hong Chang:
A new write-contention based dual-port SRAM PUF with multiple response bits per cell. ISCAS 2017: 1-4 - [c110]Miodrag Potkonjak, Gang Qu, Farinaz Koushanfar, Chip-Hong Chang:
20 Years of research on intellectual property protection. ISCAS 2017: 1-4 - [c109]Zheng Wang, Yi Chen, Aakash Patil, Chip-Hong Chang, Arindam Basu:
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability. ISCAS 2017: 1-4 - [c108]Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang:
Low-cost fortification of arbiter PUF against modeling attack. ISCAS 2017: 1-4 - [c107]Sumedh Dhabu, Chip-Hong Chang:
A novel scheme for information hiding at physical layer of wireless communications. ISOCC 2017: 256-257 - [c106]Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang:
FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability. ISQED 2017: 313-318 - [e2]Chip-Hong Chang, Ulrich Rührmair, Wei Zhang:
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2017, Dallas, TX, USA, November 3, 2017. ACM 2017, ISBN 978-1-4503-5397-7 [contents] - 2016
- [j64]Chip-Hong Chang, Tae-Hyoung Kim, Hao Yu:
Editorial. J. Circuits Syst. Comput. 25(1): 1602001:1-1602001:5 (2016) - [j63]Thian Fatt Tay, Chip-Hong Chang:
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS. IEEE Trans. Computers 65(2): 396-408 (2016) - [j62]Jiatao Ding, Jiajia Chen, Chip-Hong Chang:
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1605-1617 (2016) - [j61]Feng Feng, Jiajia Chen, Chip-Hong Chang:
Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 233-244 (2016) - [j60]Yuhao Wang, Leibin Ni, Chip-Hong Chang, Hao Yu:
DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory. IEEE Trans. Inf. Forensics Secur. 11(11): 2426-2440 (2016) - [j59]Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low:
Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1612 (2016) - [j58]Sachin Kumar, Chip-Hong Chang:
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n-1, 2n, 2n+1}. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2608-2612 (2016) - [c105]Truong Phu Truan Ho, Chip-Hong Chang:
Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption. APCCAS 2016: 9-12 - [c104]Chao Qun Liu, Yuan Cao, Chip-Hong Chang:
Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs. APCCAS 2016: 646-649 - [c103]Siarhei S. Zalivaka, Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk, Chip-Hong Chang:
Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation. ASP-DAC 2016: 533-538 - [c102]Yuan Cao, Le Zhang, Chip-Hong Chang:
Using image sensor PUF as root of trust for birthmarking of perceptual image hash. AsianHOST 2016: 1-6 - [c101]Yue Zheng, Yuan Cao, Chip-Hong Chang:
A new event-driven Dynamic Vision Sensor based Physical Unclonable Function for camera authentication in reactive monitoring system. AsianHOST 2016: 1-6 - [c100]Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy, Chip-Hong Chang, Arindam Basu:
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. ISCAS 2016: 914-917 - [c99]Sachin Kumar, Chip-Hong Chang:
A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS. ISCAS 2016: 1966-1969 - [c98]Sumedh Dhabu, Chip-Hong Chang:
A new scheme for secret-hiding in DSP circuits. ISOCC 2016: 49-50 - 2015
- [j57]Linfeng Chen, Aijiao Cui, Chip-Hong Chang:
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction. IEEE Trans. Computers 64(12): 3417-3429 (2015) - [j56]Yuan Cao, Le Zhang, Chip-Hong Chang, Shoushun Chen:
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1143-1147 (2015) - [j55]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1176-1187 (2015) - [j54]Jiajia Chen, Chip-Hong Chang, Feng Feng, Weiao Ding, Jiatao Ding:
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 224-233 (2015) - [j53]Thian Fatt Tay, Chip-Hong Chang, Leonel Sousa:
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2248-2259 (2015) - [j52]Yuan Cao, Le Zhang, Siarhei S. Zalivaka, Chip-Hong Chang, Shoushun Chen:
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2629-2640 (2015) - [j51]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell. IEEE Trans. Inf. Forensics Secur. 10(8): 1630-1642 (2015) - [c97]Sachin Kumar, Chip-Hong Chang:
A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}. ASICON 2015: 1-4 - [c96]Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf:
Efficient structural adder pipelining in transposed form FIR filters. DSP 2015: 311-314 - [c95]Li Zhang, Chip-Hong Chang:
Public key protocol for usage-based licensing of FPGA IP cores. ISCAS 2015: 25-28 - [c94]Thian Fatt Tay, Chip-Hong Chang:
A new unified modular adder/subtractor for arbitrary moduli. ISCAS 2015: 53-56 - [c93]Le Zhang, Chip-Hong Chang, Zhi-Hui Kong, Chao Qun Liu:
Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes. ISCAS 2015: 1410-1413 - 2014
- [j50]Fei Li, Chip-Hong Chang, Arindam Basu, Liter Siek:
A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory. Neurocomputing 138: 69-77 (2014) - [j49]Chip-Hong Chang, Li Zhang:
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 76-89 (2014) - [j48]Le Zhang, Zhi-Hui Kong, Chip-Hong Chang, Alessandro Cabrini, Guido Torelli:
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions. IEEE Trans. Inf. Forensics Secur. 9(6): 921-932 (2014) - [j47]Li Zhang, Chip-Hong Chang:
A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs. IEEE Trans. Inf. Forensics Secur. 9(11): 1893-1905 (2014) - [j46]Yuan Cao, Chip-Hong Chang, Shoushun Chen:
A Cluster-Based Distributed Active Current Sensing Circuit for Hardware Trojan Detection. IEEE Trans. Inf. Forensics Secur. 9(12): 2220-2231 (2014) - [c92]Li Zhang, Chip-Hong Chang:
Hardware Trojan detection with linear regression based gate-level characterization. APCCAS 2014: 256-259 - [c91]Thian Fatt Tay, Chip-Hong Chang:
New algorithm for signed integer comparison in four-moduli superset {2n, 2n -1, 2n +1, 2n+1-1}. APCCAS 2014: 519-522 - [c90]Le Zhang, Chip-Hong Chang, Alessandro Cabrini, Guido Torelli, Zhi-Hui Kong:
Leakage-resilient memory-based physical unclonable function using phase change material. ICCST 2014: 1-6 - [c89]Jiajia Chen, Chip-Hong Chang:
Design of programmable FIR filters using Canonical Double Based Number Representation. ISCAS 2014: 1183-1186 - [c88]Chip-Hong Chang, Sachin Kumar:
Area-efficient and fast sign detection for four-moduli set RNS {2n -1, 2n, 2n +1, 22n +1}. ISCAS 2014: 1540-1543 - [c87]Thian Fatt Tay, Chip-Hong Chang:
A new algorithm for single residue digit error correction in Redundant Residue Number System. ISCAS 2014: 1748-1751 - [c86]Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. ISCAS 2014: 2169-2172 - [c85]Yuan Cao, Siarhei S. Zalivaka, Le Zhang, Chip-Hong Chang, Shoushun Chen:
CMOS image sensor based physical unclonable function for smart phone security applications. ISIC 2014: 392-395 - [c84]Wei Wei, Li Zhang, Chip-Hong Chang:
A modular design of elliptic-curve point multiplication for resource constrained devices. ISIC 2014: 596-599 - [c83]Vladimir V. Sergeichik, Alexander A. Ivaniuk, Chip-Hong Chang:
Obfuscation and watermarking of FPGA designs based on constant value generators. ISIC 2014: 608-611 - 2013
- [j45]Hanhua Qian, Chip-Hong Chang, Hao Yu:
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits. Integr. 46(1): 57-68 (2013) - [j44]Jeremy Yung Shern Low, Chip-Hong Chang:
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2366-2374 (2013) - [j43]Ramya Muralidharan, Chip-Hong Chang:
Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2940-2952 (2013) - [j42]Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low:
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1936-1940 (2013) - [c82]Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu:
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. ASP-DAC 2013: 485-490 - [c81]Hanhua Qian, Chip-Hong Chang:
Microchannel splitting and scaling for thermal balancing of liquid-cooled 3DIC. ISCAS 2013: 801-804 - [c80]Yuan Cao, Chip-Hong Chang, Shoushun Chen:
Cluster-based distributed active current timer for hardware Trojan detection. ISCAS 2013: 1010-1013 - [c79]Le Zhang, Zhi-Hui Kong, Chip-Hong Chang:
PCKGen: A Phase Change Memory based cryptographic key generator. ISCAS 2013: 1444-1447 - [c78]Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang:
A signed integer programmable power-of-two scaler for {2n-1, 2n, 2n+1} RNS. ISCAS 2013: 2211-2214 - 2012
- [j41]Pak Kwong Chan, Chip-Hong Chang, Kiat Seng Yeo:
Foreword. J. Circuits Syst. Comput. 21(8) (2012) - [j40]Chip-Hong Chang, Howard C. Luong, Shanthi Pavan:
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1601-1603 (2012) - [j39]Ramya Muralidharan, Chip-Hong Chang:
Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2263-2274 (2012) - [j38]Jeremy Yung Shern Low, Chip-Hong Chang:
A VLSI Efficient Programmable Power-of-Two Scaler for 2n-1, 2n, 2n+1 RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2911-2919 (2012) - [j37]Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang:
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2945-2955 (2012) - [j36]Fei Li, Arindam Basu, Chip-Hong Chang, Avis H. Cohen:
Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 3046-3059 (2012) - [c77]Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang:
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS 2012: 272-275 - [c76]Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang:
A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. APCCAS 2012: 296-299 - [c75]Aijiao Cui, Chip-Hong Chang:
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. APCCAS 2012: 412-415 - [c74]Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang:
Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS 2012: 49-52 - [c73]Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang:
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS 2012: 1235-1238 - [c72]Li Zhang, Chip-Hong Chang:
State encoding watermarking for field authentication of sequential circuit intellectual property. ISCAS 2012: 3013-3016 - 2011
- [j35]Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang:
Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling. J. Low Power Electron. 7(1): 110-121 (2011) - [j34]Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr Talaat Abdel-Hamid:
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 678-690 (2011) - [j33]Ramya Muralidharan, Chip-Hong Chang:
Radix-8 Booth Encoded Modulo 2 n -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 982-993 (2011) - [j32]Chip-Hong Chang, Jeremy Yung Shern Low:
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2n - 1, 2n, 2n + 1. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2686-2697 (2011) - [j31]Ruimin Huang, Chip-Hong Chang, Mathias Faust, Niklas Lotze, Yiannos Manoli:
Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 916-920 (2011) - [j30]Yu Shao, Chip-Hong Chang:
Bayesian Separation With Sparsity Promotion in Perceptual Wavelet Domain for Speech Enhancement and Hybrid Speech Recognition. IEEE Trans. Syst. Man Cybern. Part A 41(2): 284-293 (2011) - [j29]Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang:
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1733-1745 (2011) - [c71]Mathias Faust, Chip-Hong Chang:
Low error bit width reduction for structural adders of FIR filters. ECCTD 2011: 713-716 - [c70]Mathias Faust, Chip-Hong Chang:
Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA. ISCAS 2011: 657-660 - [c69]Ramya Muralidharan, Chip-Hong Chang:
A simple radix-4 Booth encoded modulo 2n+1 multiplier. ISCAS 2011: 1163-1166 - [c68]Jeremy Yung Shern Low, Chip-Hong Chang:
A new RNS scaler for {2n - 1, 2n, 2n + 1}. ISCAS 2011: 1431-1434 - [c67]Aijiao Cui, Chip-Hong Chang, Li Zhang:
A hybrid watermarking scheme for sequential functions. ISCAS 2011: 2333-2336 - 2010
- [j28]Chip-Hong Chang, Mathias Faust:
On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 844-848 (2010) - [j27]Chip-Hong Chang, Aijiao Cui:
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1618-1630 (2010) - [j26]Chip-Hong Chang, Ravi Kumar Satzoda:
A Low Error and High Performance Multiplexer-Based Truncated Multiplier. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1767-1771 (2010) - [c66]Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang:
Real-time thermal management of 3D multi-core system with fine-grained cooling control. 3DIC 2010: 1-6 - [c65]Mathias Faust, Chip-Hong Chang:
Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication. ISCAS 2010: 457-460 - [c64]Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low:
A novel counter-based low complexity inner-product architecture for high speed inputs. ISCAS 2010: 705-708 - [c63]Ramya Muralidharan, Chip-Hong Chang:
Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers. ISCAS 2010: 717-720
2000 – 2009
- 2009
- [j25]Jiajia Chen, Chip-Hong Chang:
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1844-1856 (2009) - [j24]Yajuan He, Chip-Hong Chang:
A New Redundant Binary Booth Encoding for Fast 2n-Bit Multiplier Design. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1192-1201 (2009) - [c62]Aijiao Cui, Chip-Hong Chang:
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. ISCAS 2009: 29-32 - [c61]Ramya Muralidharan, Chip-Hong Chang:
Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS. ISCAS 2009: 441-444 - [c60]Jiajia Chen, Chip-Hong Chang, Ching-Chuen Jong:
Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. ISCAS 2009: 1145-1148 - [c59]Fei Li, Chip-Hong Chang, Liter Siek:
A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. ISCAS 2009: 2129-2132 - [c58]Mathias Faust, Chip-Hong Chang:
Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters. ISCAS 2009: 2185-2188 - [c57]Jiajia Chen, Chip-Hong Chang, Hanhua Qian:
New Power Index Model for Switching Power Analysis from Adder Graph of FIR filter. ISCAS 2009: 2197-2200 - 2008
- [j23]Aijiao Cui, Chip-Hong Chang, Sofiène Tahar:
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1565-1570 (2008) - [j22]Yajuan He, Chip-Hong Chang:
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1): 336-346 (2008) - [j21]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2): 559-571 (2008) - [j20]Chip-Hong Chang, Jiajia Chen, Achutavarrier Prasad Vinod:
Information Theoretic Approach to Complexity Reduction of FIR Filter Design. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2310-2321 (2008) - [c56]Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang:
High-speed and low-power serial accumulator for serial/parallel multiplier. APCCAS 2008: 176-179 - [c55]Ramya Muralidharan, Chip-Hong Chang, Ching-Chuen Jong:
A low complexity modulo 2n+1 squarer design. APCCAS 2008: 1296-1299 - [c54]Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang:
Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). ISCAS 2008: 808-811 - [c53]Aijiao Cui, Chip-Hong Chang:
Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS 2008: 2645-2648 - 2007
- [j19]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. Comput. Electr. Eng. 33(3): 195-207 (2007) - [j18]A. Prasad Vinod, Ankita Singla, Chip-Hong Chang:
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers. IET Circuits Devices Syst. 1(1): 13-20 (2007) - [j17]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1898-1907 (2007) - [j16]Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan:
A Residue-to-Binary Converter for a New Five-Moduli Set. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 1041-1049 (2007) - [j15]Yu Shao, Chip-Hong Chang:
A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System. IEEE Trans. Syst. Man Cybern. Part B 37(4): 877-889 (2007) - [c52]Aijiao Cui, Chip-Hong Chang:
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS 2007: 3687-3690 - 2006
- [c51]Jiajia Chen, Chip-Hong Chang, A. Prasad Vinod:
Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. APCCAS 2006: 756-759 - [c50]Aijiao Cui, Chip-Hong Chang:
Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS 2006: 1023-1026 - [c49]Shibu Menon, Chip-Hong Chang:
A Reconfigurable Multi-Modulus Modulo Multiplier. APCCAS 2006: 1168-1171 - [c48]A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla:
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. APCCAS 2006: 1547-1550 - [c47]A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla:
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. APCCAS 2006: 1551-1554 - [c46]Uwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster:
A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. APCCAS 2006: 1555-1558 - [c45]Chip-Hong Chang, Jiajia Chen, A. Prasad Vinod:
Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design. ISCAS 2006 - [c44]Aijiao Cui, Chip-Hong Chang:
Stego-signature at logic synthesis level for digital design IP protection. ISCAS 2006 - [c43]Yajuan He, Chip-Hong Chang:
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ISCAS 2006 - [c42]Ravi Kumar Satzoda, Chip-Hong Chang:
A fast kernel for unifying GF(p) and GF(2m) Montgomery multiplications in a scalable pipelined architecture. ISCAS 2006 - [c41]Yu Shao, Chip-Hong Chang:
A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement. ISCAS 2006 - [c40]Yu Shao, Chip-Hong Chang:
A novel hybrid neuro-wavelet system for robust speech recognition. ISCAS 2006 - [c39]Yu Shao, Chip-Hong Chang:
A generalized perceptual time-frequency subtraction method for speech enhancement. ISCAS 2006 - [c38]A. Prasad Vinod, Ankita Singla, Chip-Hong Chang:
Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. ISCAS 2006 - [c37]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
A new integrated approach to the design of low-complexity FIR filters. ISCAS 2006 - 2005
- [j14]Zhi-Hui Kong, Kiat Seng Yeo, Chip-Hong Chang:
An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. J. Circuits Syst. Comput. 14(5): 939-952 (2005) - [j13]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
Contention resolution algorithm for common subexpression elimination in digital filter design. IEEE Trans. Circuits Syst. II Express Briefs 52-II(10): 695-700 (2005) - [j12]Chip-Hong Chang, Zhi Ye, Mingyan Zhang:
Fuzzy-ART based adaptive digital watermarking scheme. IEEE Trans. Circuits Syst. Video Technol. 15(1): 65-81 (2005) - [j11]Chip-Hong Chang, Pengfei Xu, Rui Xiao, Thambipillai Srikanthan:
New adaptive color quantization method based on self-organizing maps. IEEE Trans. Neural Networks 16(1): 237-249 (2005) - [j10]Pengfei Xu, Chip-Hong Chang, Andrew P. Paplinski:
Self-organizing topological tree for online vector quantization and data clustering. IEEE Trans. Syst. Man Cybern. Part B 35(3): 515-526 (2005) - [j9]Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang:
A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 686-695 (2005) - [c36]Ravi Kumar Satzoda, Chip-Hong Chang:
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. Asia-Pacific Computer Systems Architecture Conference 2005: 693-706 - [c35]Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy:
A novel covalent redundant binary Booth encoder. ISCAS (1) 2005: 69-72 - [c34]Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar:
A novel multiplexer based truncated array multiplier. ISCAS (1) 2005: 85-88 - [c33]Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan:
A new formulation of fast diminished-one multioperand modulo 2n/+1 adder. ISCAS (1) 2005: 656-659 - [c32]Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang:
A new design method to modulo 2n-1 squaring. ISCAS (1) 2005: 664-667 - [c31]Yu Shao, Chip-Hong Chang:
A versatile speech enhancement system based on perceptual wavelet denoising. ISCAS (2) 2005: 864-867 - [c30]Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan:
A configurable dual moduli multi-operand modulo adder. ISCAS (2) 2005: 1630-1633 - [c29]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
I2CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. ISCAS (2) 2005: 1823-1826 - [c28]Yu Shao, Chip-Hong Chang:
Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. ISCAS (4) 2005: 3833-3836 - [c27]Yajuan He, Chip-Hong Chang, Jiangmin Gu:
An area efficient 64-bit square root carry-select adder for low power applications. ISCAS (4) 2005: 4082-4085 - [e1]Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang:
Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings. Lecture Notes in Computer Science 3740, Springer 2005, ISBN 3-540-29643-3 [contents] - 2004
- [j8]Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang:
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(10): 1985-1997 (2004) - [c26]Xiaoyun Deng, Chip-Hong Chang, Erwin Brandle:
A New Method for Eye Extraction from Facial Image. DELTA 2004: 29-34 - [c25]Zhi Ye, Chip-Hong Chang:
Local Search Method for FIR Filter Coefficients Synthesis. DELTA 2004: 255-260 - [c24]Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang:
Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. DELTA 2004: 407-409 - [c23]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
Efficient algorithms for common subexpression elimination in digital filter design. ICASSP (5) 2004: 137-140 - [c22]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
HWP: a new insight into canonical signed digit. ISCAS (5) 2004: 201-204 - [c21]Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. ISCAS (3) 2004: 481-484 - [c20]Pengfei Xu, Chip-Hong Chang:
Self-organizing topological tree. ISCAS (5) 2004: 732-735 - [c19]Chip-Hong Chang, Pengfei Xu:
Frequency sensitive self-organizing maps and its application in color quantization. ISCAS (5) 2004: 804-807 - [c18]Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang:
Design of residue-to-binary converter for a new 5-moduli superset residue number system. ISCAS (2) 2004: 841-844 - 2003
- [c17]Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan:
An adaptive initialization technique for color quantization by self organizing feature map. ICASSP (3) 2003: 477-480 - [c16]Jiangmin Gu, Chip-Hong Chang:
Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits. ICASSP (2) 2003: 661-664 - [c15]Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang:
A novel hybrid pass logic with static CMOS output drive full-adder cell. ISCAS (5) 2003: 317-320 - [c14]Jiangmin Gu, Chip-Hong Chang:
Ultra low voltage, low power 4-2 compressor for high speed multiplications. ISCAS (5) 2003: 321-324 - [c13]Shibu Menon, Chip-Hong Chang, Rui Xiao:
FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging. ISCAS (2) 2003: 452-455 - [c12]Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang:
Design of a high speed reverse converter for a new 4-moduli set residue number system. ISCAS (4) 2003: 520-523 - [c11]Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan:
New efficient residue-to-binary converters for 4-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1}. ISCAS (4) 2003: 536-539 - 2002
- [j7]Chip-Hong Chang, Hui Tian, Thambipillai Srikanthan, Chai-Soon Lim:
Field programable gate array based architecture for real time image segmentation by region growing algorithm. J. Electronic Imaging 11(4): 469-478 (2002) - [j6]Chip-Hong Chang, Bogdan J. Falkowski:
Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix. VLSI Design 14(3): 259-271 (2002) - [c10]Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan:
A MSB-biased self-organizing feature map for still color image compression. APCCAS (2) 2002: 85-88 - [c9]Chip-Hong Chang, Zhi Ye, Mingyan Zhang:
Fuzzy-ART based digital watermarking scheme. APCCAS (1) 2002: 423-426 - [c8]Hui Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang:
An efficient architecture for adaptive progressive thresholding. APCCAS (1) 2002: 513-516 - [c7]Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan:
On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. DELTA 2002: 321-325 - [c6]Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo:
An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468 - 2000
- [j5]Bogdan J. Falkowski, Chip-Hong Chang:
Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions. VLSI Design 11(4): 311-320 (2000)
1990 – 1999
- 1999
- [j4]Bogdan J. Falkowski, Chip-Hong Chang:
An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions. VLSI Design 9(2): 135-146 (1999) - [c5]Chip-Hong Chang, Bogdan J. Falkowski:
Reed-Muller weight and literal vectors for NPN classification. ISCAS (1) 1999: 379-382 - [c4]Bogdan J. Falkowski, Chip-Hong Chang:
Optimization of partially-mixed-polarity Reed-Muller expansions. ISCAS (1) 1999: 383-386 - 1998
- [j3]Chip-Hong Chang, C.-K. Lin, Neil Goldsman, Isaak D. Mayergoyz:
Spherical Harmonic Modeling of a 0.05 μm Base BJT: A Comparison with Monte Carlo and Asymptotic Analysis. VLSI Design 8(1-4): 147-151 (1998) - 1997
- [j2]Bogdan J. Falkowski, Chip-Hong Chang:
Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions. IEEE Trans. Computers 46(11): 1272-1279 (1997) - 1995
- [c3]Chip-Hong Chang, Bogdan J. Falkowski:
Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. ASP-DAC 1995 - [c2]Bogdan J. Falkowski, Chip-Hong Chang:
Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. ISCAS 1995: 2168-2171 - 1994
- [c1]Bogdan J. Falkowski, Chip-Hong Chang:
Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. ISCAS 1994: 197-200 - 1993
- [j1]M. A. Do, Chip-Hong Chang:
Design and Performance of a New Multi-Lane AVI System. J. Intell. Transp. Syst. 1(2): 151-166 (1993)
Coauthor Index
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