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2020 – today
- 2024
[j60]Shun-Hua Yang, Shi-Yu Huang
:
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme. J. Electron. Test. 40(1): 31-43 (2024)- [j59]Ching-Yi Wen, Shi-Yu Huang:
Instant Test and Repair for TSVs using Differential Signaling. J. Electron. Test. 40(2): 275-287 (2024) - [j58]Shu-Yu Chang, Shi-Yu Huang:
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1253-1262 (2024) - [c87]Cheng-Wen Wu, Shi-Yu Huang:
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. ETS 2024: 1-2 - 2023
- [j57]Yung-Chuan Su, Shi-Yu Huang:
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2761-2765 (2023) - [j56]Lin Liu, Lai Chi, Shi-Yu Huang, Ka-Yi Yeh:
Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2776-2780 (2023) - [j55]Yung-Chuan Su, Shi-Yu Huang:
A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 343-354 (2023) - [c86]Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer:
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. FPL 2023: 294-298 - [c85]Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang:
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. ITC-Asia 2023: 1-6 - [c84]Chen-Lin Tsai, Shi-Yu Huang:
Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test. ITC-Asia 2023: 1-6 - [c83]Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang:
Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL. MWSCAS 2023: 792-796 - [c82]Ont-Derh Lin, Shi-Yu Huang:
Cell-Based Aging Sensor Using Built-In Speed Grading. NorCAS 2023: 1-6 - [i2]Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer:
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. CoRR abs/2306.11330 (2023) - 2022
- [j54]Wei-Hao Chen, Shi-Yu Huang:
On-Chip Jitter Learning for PLL. IEEE Des. Test 39(4): 58-63 (2022) - [j53]Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Scott Hauck, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark S. Neubauer, Isobel Ojalvo, Savannah Thais, Matthew Trahms:
Graph Neural Networks for Charged Particle Tracking on FPGAs. Frontiers Big Data 5: 828666 (2022) - [j52]Jun-Yu Yang, Shi-Yu Huang:
Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1563-1572 (2022) - [j51]Jun-Yu Yang, Shi-Yu Huang:
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2337-2347 (2022) - [c81]Yung-Chuan Su, Shi-Yu Huang:
Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter. ISOCC 2022: 45-46 - [c80]Chen-Lin Tsai, Shi-Yu Huang:
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. ITC 2022: 137-144 - 2021
- [j50]Wei Chu, Shi-Yu Huang:
Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor. IEEE Trans. Emerg. Top. Comput. 9(2): 735-744 (2021) - [c79]Yi-Hsuan Lee, Shi-Yu Huang:
Rigorous Test Flow for PLL to Identify Weak Devices. ITC-Asia 2021: 1-6 - [c78]Chen-Lin Tsai, Wei-Hao Chen, Shi-Yu Huang:
A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal. ITC-Asia 2021: 1-6 - [i1]Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark S. Neubauer, Isobel Ojalvo, Savannah Thais:
Graph Neural Networks for Charged Particle Tracking on FPGAs. CoRR abs/2112.02048 (2021) - 2020
- [j49]Chia-Hua Wu, Shi-Yu Huang, Yung-Fa Chou, Ding-Ming Kwai:
Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Des. Test 37(4): 101-107 (2020) - [j48]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng:
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3044-3055 (2020) - [c77]Shi-Yu Huang:
Overview of On-Chip Performance Monitors for Clock Signals. ATS 2020: 1-4 - [c76]Jun-Yu Yang, Shi-Yu Huang:
Fault and Soft Error Tolerant Delay-Locked Loop. ATS 2020: 1-6 - [c75]Wei Chu, Wei-Hao Chen, Shi-Yu Huang:
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. ICCD 2020: 457-460 - [c74]Derek Lin, Jun-Yu Yang, Shi-Yu Huang:
A Voting Phase Detector Design with Mitigated Process Variation. ISOCC 2020: 91-92 - [c73]Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang:
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. ITC 2020: 1-8
2010 – 2019
- 2019
- [j47]Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang:
A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop. IEEE Access 7: 97928-97937 (2019) - [j46]Guan-Hao Lian, Wei-yi Chen, Shi-Yu Huang:
Cloud-Based Online Ageing Monitoring for IoT Devices. IEEE Access 7: 135964-135971 (2019) - [c72]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng:
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC 2019: 341-346 - [c71]Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang:
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. DAC 2019: 231 - [c70]Wei Chu, Shi-Yu Huang:
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. ITC 2019: 1-10 - [c69]Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian:
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC 2019: 1-4 - [c68]Wei Chu, Shi-Yu Huang:
Online Testing of Clock Delay Faults in a Clock Network. ITC-Asia 2019: 163-168 - [c67]Wei Chu, Shi-Yu Huang:
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling. NEWCAS 2019: 1-4 - 2018
- [j45]Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2087-2097 (2018) - [c66]Yu-Chi Wei, Shi-Yu Huang:
A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL. ISOCC 2018: 90-91 - [c65]Cheng-En Lee, Shi-Yu Huang:
A Cell-Based Fractional-N Phase-Locked Loop Compiler. SMACD 2018: 273-276 - 2017
- [c64]Guan-Hao Lian, Shi-Yu Huang, Wei-yi Chen:
Cloud-Based PVT Monitoring System for IoT Devices. ATS 2017: 76-81 - [c63]Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
DLL-Assisted Clock Synchronization Method for Multi-Die ICs. ICCD 2017: 473-476 - [c62]Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai:
Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI 2017: 7-12 - [c61]Shi-Yu Huang:
Test strategies for the clock and power distribution networks in a multi-die IC. VLSI-DAT 2017: 1-2 - 2016
- [j44]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng:
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33(2): 9-16 (2016) - [j43]Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng:
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33(6): 23-30 (2016) - [c60]Shi-Yu Huang:
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects. ATS 2016: 80-85 - [c59]Shi-Yu Huang, Chih-Chieh Zheng:
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs. ATS 2016: 221-226 - [c58]Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Testing of small delay faults in a clock network. ETS 2016: 1-6 - [c57]Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng:
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS 2016: 125-129 - [c56]Pei-Ching Huang, Shi-Yu Huang:
Cell-based delay locked loop compiler. ISOCC 2016: 91-92 - [c55]Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng:
Online slack-time binning for IO-registered die-to-die interconnects. ITC 2016: 1-8 - 2015
- [j42]Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1836-1846 (2015) - [j41]Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2039-2048 (2015) - [j40]Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee:
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems. ACM Trans. Design Autom. Electr. Syst. 20(2): 22:1-22:27 (2015) - [c54]Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Temperature-aware online testing of power-delivery TSVs. 3DIC 2015: TS10.3.1-TS10.3.6 - [c53]Jinn-Yann Liu, Shi-Yu Huang, Ta-Shun Chu:
Cell-based programmable phase shifter design for pulsed radar SoC. ASICON 2015: 1-4 - [c52]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng:
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE 2015: 924-927 - [c51]Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Monitoring the delay of long interconnects via distributed TDC. ITC 2015: 1-9 - 2014
- [j39]Shi-Yu Huang, Li-Ren Huang:
PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning. IEEE Des. Test 31(4): 36-42 (2014) - [j38]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 476-488 (2014) - [j37]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1258-1268 (2014) - [j36]Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao:
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 621-630 (2014) - [c50]Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS 2014: 162-167 - [c49]Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS 2014: 1-2 - 2013
- [j35]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013) - [j34]Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1265-1273 (2013) - [j33]Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng:
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1440-1444 (2013) - [j32]Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou:
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 908-917 (2013) - [j31]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [j30]Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 443-453 (2013) - [j29]Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang:
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2240-2249 (2013) - [j28]Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng:
Cell-Based Process Resilient Multiphase Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2348-2352 (2013) - [c48]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
Mid-bond Interposer Wire Test. Asian Test Symposium 2013: 153-158 - [c47]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS 2013: 67-72 - [c46]Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC 2013: 1-8 - [c45]Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Worst-case IR-drop monitoring with 1GHz sampling rate. VLSI-DAT 2013: 1-4 - 2012
- [j27]Feng-Cheng Huang, Shi-Yu Huang, Ji-Wei Ker, Yung-Chang Chen:
High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. IEEE Trans. Circuits Syst. Video Technol. 22(3): 340-351 (2012) - [c44]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs. Asian Test Symposium 2012: 43-48 - [c43]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036 - [c42]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10 - [c41]Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng:
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. VLSI-DAT 2012: 1-4 - [c40]Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu:
A UWB IR timed-array radar using time-shifted direct-sampling architecture. VLSIC 2012: 54-55 - 2011
- [j26]Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu:
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Des. Test Comput. 28(4): 88-97 (2011) - [j25]Bor-Woei Kuo, Hsun-Hao Chang, Yung-Chang Chen, Shi-Yu Huang:
A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map. J. Robotics 2011: 257852:1-257852:12 (2011) - [j24]Cheng-Hung Lo, Shi-Yu Huang:
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. IEEE J. Solid State Circuits 46(3): 695-704 (2011) - [j23]Hsuan-Jung Hsu, Shi-Yu Huang:
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 165-170 (2011) - [c39]Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh:
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC 2011: 47-52 - [c38]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - [c37]Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen:
Black-box leakage power modeling for cell library and SRAM compiler. DATE 2011: 637-642 - [c36]Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao:
A fully cell-based design for timing measurement of memory. ITC 2011: 1-10 - 2010
- [j22]Chao-Wen Tzeng, Shi-Yu Huang:
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 834-839 (2010) - [c35]Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang:
PAC duo system power estimation at ESL. ASP-DAC 2010: 815-820 - [c34]Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394 - [c33]Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee:
Power aware SID-based simulator for embedded multicore DSP subsystems. CODES+ISSS 2010: 95-104 - [c32]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348
2000 – 2009
- 2009
- [j21]Ya-Chun Lai, Shi-Yu Huang:
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT). IEEE J. Solid State Circuits 44(2): 642-649 (2009) - [j20]Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu:
Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM. IEEE J. Solid State Circuits 44(10): 2817-2823 (2009) - [j19]Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang:
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 764-769 (2009) - [j18]Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1756-1766 (2009) - [c31]Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: An X-Fill method for quick-and-cool scan test. DATE 2009: 1142-1147 - 2008
- [j17]Chao-Wen Tzeng, Shi-Yu Huang:
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Des. Test Comput. 25(2): 132-140 (2008) - [j16]Ya-Chun Lai, Shi-Yu Huang:
X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs. IEEE J. Solid State Circuits 43(9): 1964-1971 (2008) - [j15]Ya-Chun Lai, Shi-Yu Huang:
A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 1031-1035 (2008) - [j14]Shin-Pao Cheng, Shi-Yu Huang:
A low-power SRAM for Viterbi decoder in wireless communication. IEEE Trans. Consumer Electron. 54(2): 290-295 (2008) - [j13]Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang:
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13(1): 9:1-9:27 (2008) - [c30]Chao-Wen Tzeng, Shi-Yu Huang:
Two-Gear Low-Power Scan Test. ATS 2008: 337-342 - 2007
- [j12]Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang:
Robust paradigm for diagnosing hold-time faults in scan chains. IET Comput. Digit. Tech. 1(6): 706-715 (2007) - [j11]Chao-Wen Tzeng, Shi-Yu Huang:
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 690-694 (2007) - [c29]Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang:
Built-In Speed Grading with a Process-Tolerant ADPLL. ATS 2007: 384-392 - [c28]Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang:
RT-level vector selection for realistic peak power simulation. ACM Great Lakes Symposium on VLSI 2007: 576-581 - 2006
- [j10]Yu-Chiun Lin, Shi-Yu Huang:
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. J. Electron. Test. 22(2): 151-159 (2006) - [c27]Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495 - 2005
- [j9]Ying-Chieh Chuang, Shih-Fang Chen, Shi-Yu Huang, Ya-Chin King:
Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. IEEE Trans. Consumer Electron. 51(4): 1212-1217 (2005) - [c26]Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang:
Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371 - [c25]Jheng-Syun Yang, Shi-Yu Huang:
Quick Scan Chain Diagnosis Using Signal Profiling. ICCD 2005: 157-160 - [c24]Shin-Pao Cheng, Shi-Yu Huang:
A low-power SRAM design using quiet-bitline architecture. MTDT 2005: 135-139 - 2004
- [c23]Shi-Yu Huang:
A Fading Algorithm For Sequential Fault Diagnosis. DFT 2004: 139-147 - 2003
- [j8]Shi-Yu Huang:
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. J. Electron. Test. 19(2): 161-172 (2003) - [j7]Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu:
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19(4): 571-587 (2003) - [c22]Yu-Chiun Lin, Shi-Yu Huang:
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. Asian Test Symposium 2003: 38-43 - [c21]MingHung Lee, TingTing Hwang, Shi-Yu Huang:
Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153 - [c20]Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang:
Combinational circuit fault diagnosis using logic emulation. ISCAS (5) 2003: 549-552 - 2002
- [j6]Shi-Yu Huang:
Improving the Timing of Extended Finite State Machines Via Catalyst. VLSI Design 15(3): 629-635 (2002) - [c19]Shi-Yu Huang:
Diagnosis Of Byzantine Open-Segment Faults. Asian Test Symposium 2002: 248- - [c18]Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang:
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128 - [c17]Shi-Yu Huang:
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. VTS 2002: 193-200 - 2001
- [j5]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001) - [c16]Shi-Yu Huang:
Towards the logic defect diagnosis for partial-scan designs. ASP-DAC 2001: 313-318 - [c15]Shi-Yu Huang:
On speeding up extended finite state machines using catalyst circuitry. ASP-DAC 2001: 583-588 - [c14]Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- - [c13]Shi-Yu Huang:
On Improving the Accuracy Of Multiple Defect Diagnosis. VTS 2001: 34-41 - 2000
- [j4]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000) - [c12]Shi-Yu Huang, Sudhakar M. Reddy:
High Performance/Delay Testing. Asian Test Symposium 2000: 490
1990 – 1999
- 1999
- [j3]Shi-Yu Huang, Kwang-Ting Cheng:
ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1341-1352 (1999) - [j2]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1376-1384 (1999) - [j1]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: A new methodology for fault grading. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1487-1495 (1999) - 1998
- [c11]Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho:
A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556 - [c10]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu:
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637 - 1997
- [c9]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC 1997: 455-460 - [c8]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng:
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981 - [c7]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Incremental logic rectification. VTS 1997: 143-149 - 1996
- [c6]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee:
Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164 - [c5]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Error Correction Based on Verification Techniques. DAC 1996: 258-261 - [c4]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277- - [c3]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee:
A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72 - [c2]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser:
An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874 - 1995
- [c1]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686
Coauthor Index
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